sin_sample.hier_info

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· HIER_INFO 代码 · 共 274 行

|sin_sample
data_da[0] <= trans_ad_da:inst3.data_da[0]
data_da[1] <= trans_ad_da:inst3.data_da[1]
data_da[2] <= trans_ad_da:inst3.data_da[2]
data_da[3] <= trans_ad_da:inst3.data_da[3]
data_da[4] <= trans_ad_da:inst3.data_da[4]
data_da[5] <= trans_ad_da:inst3.data_da[5]
data_da[6] <= trans_ad_da:inst3.data_da[6]
data_da[7] <= trans_ad_da:inst3.data_da[7]
data_da[8] <= trans_ad_da:inst3.data_da[8]
data_da[9] <= trans_ad_da:inst3.data_da[9]
data_da[10] <= trans_ad_da:inst3.data_da[10]
data_da[11] <= trans_ad_da:inst3.data_da[11]
data_da[12] <= trans_ad_da:inst3.data_da[12]
data_da[13] <= trans_ad_da:inst3.data_da[13]
inclk0 => inst2.IN0


|sin_sample|trans_ad_da:inst3
data_ad[0] => LessThan1.IN28
data_ad[0] => LessThan0.IN28
data_ad[0] => data_da[0].DATAIN
data_ad[1] => LessThan1.IN27
data_ad[1] => LessThan0.IN27
data_ad[1] => data_da[1].DATAIN
data_ad[2] => LessThan1.IN26
data_ad[2] => LessThan0.IN26
data_ad[2] => data_da[2].DATAIN
data_ad[3] => LessThan1.IN25
data_ad[3] => LessThan0.IN25
data_ad[3] => data_da[3].DATAIN
data_ad[4] => LessThan1.IN24
data_ad[4] => LessThan0.IN24
data_ad[4] => data_da[4].DATAIN
data_ad[5] => LessThan1.IN23
data_ad[5] => LessThan0.IN23
data_ad[5] => data_da[5].DATAIN
data_ad[6] => LessThan1.IN22
data_ad[6] => LessThan0.IN22
data_ad[6] => data_da[6].DATAIN
data_ad[7] => LessThan1.IN21
data_ad[7] => LessThan0.IN21
data_ad[7] => data_da[7].DATAIN
data_ad[8] => LessThan1.IN20
data_ad[8] => LessThan0.IN20
data_ad[8] => data_da[8].DATAIN
data_ad[9] => LessThan1.IN19
data_ad[9] => LessThan0.IN19
data_ad[9] => data_da[9].DATAIN
data_ad[10] => LessThan1.IN18
data_ad[10] => LessThan0.IN18
data_ad[10] => data_da[10].DATAIN
data_ad[11] => LessThan1.IN17
data_ad[11] => LessThan0.IN17
data_ad[11] => data_da[11].DATAIN
data_ad[12] => LessThan1.IN16
data_ad[12] => LessThan0.IN16
data_ad[12] => data_da[12].DATAIN
data_ad[13] => Add1.IN2
data_ad[13] => Add0.IN2
data_ad[13] => LessThan1.IN15
data_ad[13] => LessThan0.IN15
data_da[0] <= data_ad[0].DB_MAX_OUTPUT_PORT_TYPE
data_da[1] <= data_ad[1].DB_MAX_OUTPUT_PORT_TYPE
data_da[2] <= data_ad[2].DB_MAX_OUTPUT_PORT_TYPE
data_da[3] <= data_ad[3].DB_MAX_OUTPUT_PORT_TYPE
data_da[4] <= data_ad[4].DB_MAX_OUTPUT_PORT_TYPE
data_da[5] <= data_ad[5].DB_MAX_OUTPUT_PORT_TYPE
data_da[6] <= data_ad[6].DB_MAX_OUTPUT_PORT_TYPE
data_da[7] <= data_ad[7].DB_MAX_OUTPUT_PORT_TYPE
data_da[8] <= data_ad[8].DB_MAX_OUTPUT_PORT_TYPE
data_da[9] <= data_ad[9].DB_MAX_OUTPUT_PORT_TYPE
data_da[10] <= data_ad[10].DB_MAX_OUTPUT_PORT_TYPE
data_da[11] <= data_ad[11].DB_MAX_OUTPUT_PORT_TYPE
data_da[12] <= data_ad[12].DB_MAX_OUTPUT_PORT_TYPE
data_da[13] <= data_da~1.DB_MAX_OUTPUT_PORT_TYPE


|sin_sample|lpm_rom0:inst
address[0] => address[0]~4.IN1
address[1] => address[1]~3.IN1
address[2] => address[2]~2.IN1
address[3] => address[3]~1.IN1
address[4] => address[4]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a


|sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ug81:auto_generated.address_a[0]
address_a[1] => altsyncram_ug81:auto_generated.address_a[1]
address_a[2] => altsyncram_ug81:auto_generated.address_a[2]
address_a[3] => altsyncram_ug81:auto_generated.address_a[3]
address_a[4] => altsyncram_ug81:auto_generated.address_a[4]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ug81:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ug81:auto_generated.q_a[0]
q_a[1] <= altsyncram_ug81:auto_generated.q_a[1]
q_a[2] <= altsyncram_ug81:auto_generated.q_a[2]
q_a[3] <= altsyncram_ug81:auto_generated.q_a[3]
q_a[4] <= altsyncram_ug81:auto_generated.q_a[4]
q_a[5] <= altsyncram_ug81:auto_generated.q_a[5]
q_a[6] <= altsyncram_ug81:auto_generated.q_a[6]
q_a[7] <= altsyncram_ug81:auto_generated.q_a[7]
q_a[8] <= altsyncram_ug81:auto_generated.q_a[8]
q_a[9] <= altsyncram_ug81:auto_generated.q_a[9]
q_a[10] <= altsyncram_ug81:auto_generated.q_a[10]
q_a[11] <= altsyncram_ug81:auto_generated.q_a[11]
q_a[12] <= altsyncram_ug81:auto_generated.q_a[12]
q_a[13] <= altsyncram_ug81:auto_generated.q_a[13]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|sin_sample|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ug81:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT


|sin_sample|address_gen:inst1
clk => address[4]~reg0.CLK
clk => address[3]~reg0.CLK
clk => address[2]~reg0.CLK
clk => address[1]~reg0.CLK
clk => address[0]~reg0.CLK
address[0] <= address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[1] <= address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[2] <= address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[3] <= address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[4] <= address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE