prev_cmp_sin_sample.fit.qmsg

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· QMSG 代码 · 共 42 行 · 第 1/5 页

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "14 unused 3.30 0 14 0 " "Info: Number of I/O pins in group: 14 (unused VREF, 3.30 VCCIO, 0 input, 14 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 6 31 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 6 total pin(s) used --  31 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 43 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 40 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.30V 9 30 " "Info: I/O bank number 5 does not use VREF pins and has 3.30V VCCIO pins. 9 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.30V 7 29 " "Info: I/O bank number 6 does not use VREF pins and has 3.30V VCCIO pins. 7 total pin(s) used --  29 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 40 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 43 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.295 ns register register " "Info: Estimated most critical path is register to register delay of 5.295 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] 1 REG LAB_X33_Y12 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X33_Y12; Fanout = 9; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.443 ns) + CELL(0.177 ns) 1.620 ns sld_hub:sld_hub_inst\|node_ena~10 2 COMB LAB_X36_Y13 6 " "Info: 2: + IC(1.443 ns) + CELL(0.177 ns) = 1.620 ns; Loc. = LAB_X36_Y13; Fanout = 6; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~10'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.620 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.131 ns) + CELL(0.544 ns) 2.295 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr~22 3 COMB LAB_X36_Y13 1 " "Info: 3: + IC(0.131 ns) + CELL(0.544 ns) = 2.295 ns; Loc. = LAB_X36_Y13; Fanout = 1; COMB Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr~22'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.675 ns" { sld_hub:sld_hub_inst|node_ena~10 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~22 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.693 ns) + CELL(0.521 ns) 3.509 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr 4 COMB LAB_X38_Y13 2 " "Info: 4: + IC(0.693 ns) + CELL(0.521 ns) = 3.509 ns; Loc. = LAB_X38_Y13; Fanout = 2; COMB Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.214 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~22 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.475 ns) + CELL(0.517 ns) 4.501 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~65 5 COMB LAB_X38_Y13 2 " "Info: 5: + IC(0.475 ns) + CELL(0.517 ns) = 4.501 ns; Loc. = LAB_X38_Y13; Fanout = 2; COMB Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~65'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.992 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~65 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 375 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.581 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]~66 6 COMB LAB_X38_Y13 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 4.581 ns; Loc. = LAB_X38_Y13; Fanout = 2; COMB Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]~66'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~65 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~66 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 375 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.661 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]~67 7 COMB LAB_X38_Y13 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 4.661 ns; Loc. = LAB_X38_Y13; Fanout = 2; COMB Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]~67'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~66 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~67 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 375 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 4.741 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]~68 8 COMB LAB_X38_Y13 1 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 4.741 ns; Loc. = LAB_X38_Y13; Fanout = 1; COMB Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]~68'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~67 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~68 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 375 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 5.199 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]~64 9 COMB LAB_X38_Y13 1 " "Info: 9: + IC(0.000 ns) + CELL(0.458 ns) = 5.199 ns; Loc. = LAB_X38_Y13; Fanout = 1; COMB Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]~64'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~68 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~64 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 375 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 5.295 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\] 10 REG LAB_X38_Y13 16 " "Info: 10: + IC(0.000 ns) + CELL(0.096 ns) = 5.295 ns; Loc. = LAB_X38_Y13; Fanout = 16; REG Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~64 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 375 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.553 ns ( 48.22 % ) " "Info: Total cell delay = 2.553 ns ( 48.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.742 ns ( 51.78 % ) " "Info: Total interconnect delay = 2.742 ns ( 51.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.295 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~22 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~65 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~66 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~67 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~68 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~64 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}