prev_cmp_sin_sample.fit.qmsg

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· QMSG 代码 · 共 42 行 · 第 1/5 页

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~22 " "Info: Destination node lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~22" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~22 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~22 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1 " "Info: Destination node lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~10 " "Info: Destination node lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~10" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~10 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~10 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_reg\[11\]~1592 " "Info: Destination node lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_reg\[11\]~1592" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 409 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[11]~1592 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[11]~1592 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}