sin_sample.map.qmsg

EP2C CYCONLY 系列的FPGA时钟测试程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 24 14:40:26 2008 " "Info: Processing started: Mon Mar 24 14:40:26 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sin_sample -c sin_sample " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin_sample -c sin_sample" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sin_sample.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sin_sample.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sin_sample " "Info: Found entity 1: sin_sample" {  } { { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "address_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file address_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_gen " "Info: Found entity 1: address_gen" {  } { { "address_gen.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/address_gen.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ad_da.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ad_da.v" { { "Info" "ISGN_ENTITY_NAME" "1 ad_da " "Info: Found entity 1: ad_da" {  } { { "ad_da.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/ad_da.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sin_sample " "Info: Elaborating entity \"sin_sample\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "trans_ad_da.v 1 1 " "Warning: Using design file trans_ad_da.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 trans_ad_da " "Info: Found entity 1: trans_ad_da" {  } { { "trans_ad_da.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/trans_ad_da.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans_ad_da trans_ad_da:inst3 " "Info: Elaborating entity \"trans_ad_da\" for hierarchy \"trans_ad_da:inst3\"" {  } { { "sin_sample.bdf" "inst3" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 160 544 712 256 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 trans_ad_da.v(37) " "Warning (10230): Verilog HDL assignment warning at trans_ad_da.v(37): truncated value with size 32 to match size of target (14)" {  } { { "trans_ad_da.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/trans_ad_da.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.v 1 1 " "Warning: Using design file lpm_rom0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/lpm_rom0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst\"" {  } { { "sin_sample.bdf" "inst" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 48 312 472 128 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/71/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.v" "altsyncram_component" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/lpm_rom0.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/lpm_rom0.v" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ug81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ug81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ug81 " "Info: Found entity 1: altsyncram_ug81" {  } { { "db/altsyncram_ug81.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_ug81.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ug81 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated " "Info: Elaborating entity \"altsyncram_ug81\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ug81:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_gen address_gen:inst1 " "Info: Elaborating entity \"address_gen\" for hierarchy \"address_gen:inst1\"" {  } { { "sin_sample.bdf" "inst1" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 40 96 256 136 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 address_gen.v(39) " "Warning (10230): Verilog HDL assignment warning at address_gen.v(39): truncated value with size 32 to match size of target (5)" {  } { { "address_gen.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/address_gen.v" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "5 " "Info: Implemented 5 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "14 " "Info: Implemented 14 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 24 14:40:30 2008 " "Info: Processing ended: Mon Mar 24 14:40:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}