address_gen.v.bak

EP2C CYCONLY 系列的FPGA时钟测试程序

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// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Wed Feb 27 20:22:44 2008

//  Module Declaration
module address_gen
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	clk, address
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk;
	output [4:0] address;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg [4:0] address;
	always @(posedge clk)
		begin
			address<=address+1;
		end
endmodule