sin_sample.map.summary

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Mon Mar 24 14:40:30 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : sin_sample
Top-level Entity Name : sin_sample
Family : Cyclone II
Total logic elements : 5
    Total combinational functions : 5
    Dedicated logic registers : 5
Total registers : 5
Total pins : 15
Total virtual pins : 0
Total memory bits : 448
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0