trans_ad_da.v.bak

EP2C CYCONLY 系列的FPGA时钟测试程序

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 7.1 (Build Build 156 04/30/2007)
// Created on Sat Dec 15 11:49:12 2007

//  Module Declaration
module trans_ad_da
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	data_ad, data_da
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [13:0] data_ad;
	output [13:0] data_da;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

	assign data_da=(data_ad>=0 & data_ad<8192)? (data_ad+8192):	(data_ad-8192);
	
endmodule