sin_sample.qsf

EP2C CYCONLY 系列的FPGA时钟测试程序

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		sin_sample_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY sin_sample
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:15:39  FEBRUARY 27, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_global_assignment -name USER_LIBRARIES "d:\\altera\\71\\ip\\fir_compiler\\lib/"
set_global_assignment -name BDF_FILE sin_sample.bdf
set_global_assignment -name VERILOG_FILE address_gen.v
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE sin_sample.vwf
set_location_assignment PIN_G18 -to data_da[11]
set_location_assignment PIN_E19 -to data_da[10]
set_location_assignment PIN_G17 -to data_da[9]
set_location_assignment PIN_H17 -to data_da[8]
set_location_assignment PIN_J15 -to data_da[7]
set_location_assignment PIN_H18 -to data_da[6]
set_location_assignment PIN_N22 -to data_da[5]
set_location_assignment PIN_N21 -to data_da[4]
set_location_assignment PIN_P15 -to data_da[3]
set_location_assignment PIN_N15 -to data_da[2]
set_location_assignment PIN_P17 -to data_da[1]
set_location_assignment PIN_P18 -to data_da[0]
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_location_assignment PIN_F20 -to inclk0
set_global_assignment -name VERILOG_FILE ad_da.v
set_global_assignment -name VECTOR_TABLE_OUTPUT_FILE ../../sin_sample.sim.tbl
set_global_assignment -name ZIP_VECTOR_WAVEFORM_FILE ../../sin_sample.sim.cvwf
set_location_assignment PIN_E18 -to data_da[13]
set_location_assignment PIN_G20 -to data_da[12]