tendiv.v

由单片机和CPLD共同构成7位数字频率计

module TenDiv(F10Div,Clock);

input Clock;
output F10Div;

reg [3:0] FOut;


always @(posedge Clock)
    if( ___________ )
        _______________;
    else
        _______________ ;

assign F10Div = FOut[3] ;

endmodule