divstream.v

来自「由单片机和CPLD共同构成7位数字频率计」· Verilog 代码 · 共 27 行

module DivStream(F0p8Hz,Clock);

input Clock; //8MHz

output F0p8Hz;

wire F800KHz,F80KHz,F8KHz;
wire F800Hz,F80HzW,F8HzW;
wire F0p8HzW;

TenDiv  DFto800KHz(F800KHz,Clock);
TenDiv  DFto80KHz(F80KHz,F800KHz);
TenDiv  DFto8KHz(F8KHz,F80KHz);
TenDiv  DFto800Hz(F800Hz,F8KHz);
TenDiv  DFto80Hz(F80HzW,F800Hz);
TenDiv  DFto8Hz(F8HzW,F80HzW);
TenDiv  DFto0p8Hz(F0p8HzW,F8HzW);

assign   F0p8Hz = F0p8HzW;


endmodule