__projnav.log

8 Channel Digital Volt Meter

ISE Auto-Make Log File
-----------------------

Updating: Simulate Post-Fit VHDL Model

Starting: 'exewrap -tapkeep -mode pipe -command xilperl __checkModelSim.pl'


Starting: 'xilperl __checkModelSim.pl '


EXEWRAP detected that program 'xilperl' completed successfully.

Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command tsim top_level top_level.nga'


Starting: 'tsim top_level top_level.nga '


Release 4.1.03i_cr2early - Timing Simulation Interface E
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Creating NGA for simulation.
EXEWRAP detected that program 'tsim' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_ngaTOvhdsim_pr_exewrap.rsp'


Creating TCL Process
Starting: 'ngd2vhdl -f _ngaTOvhdsim_pr_exe.rsp'


Release 4.1.03i_cr2early - ngd2vhdl E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
ngd2vhdl: Reading design top_level.nga ...
ngd2vhdl: Specializing design ...
ngd2vhdl:   Flattening design ...
ngd2vhdl:   Flattening design completed.
ngd2vhdl: Specializing design completed.

ngd2vhdl: Processing design ...
ngd2vhdl:   Preping physical only global signals ...
ngd2vhdl:   Preping design's networks ...
ngd2vhdl:   Preping design's macros ...
ngd2vhdl: Preping design completed.

ngd2vhdl: Writing VHDL netlist top_level_timesim.vhd ...
ngd2vhdl: Setting external property filter file to
C:/xilinx_webpack/data/xdm2vhdl.prp.
ngd2vhdl: Writing file top_level_timesim.vhd completed.

ngd2vhdl: Writing VHDL SDF file top_level_timesim.sdf ...
ngd2vhdl: Writing file top_level_timesim.sdf completed.

Tcl c:/xilinx_webpack/data/projnav/_ngaTOvxsim_pr.tcl detected that program 'ngd2vhdl -f _ngaTOvhdsim_pr_exe.rsp' completed successfully.

Created top_level_timesim.vhd 
Done: completed successfully.

Starting: 'exewrap @__createPostDo_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Launching: 'exewrap @_msim_simPostRouteVhdlModel_exewrap.rsp'