gepan.vhd

来自「VGA彩色信号控制器设计：用VHDL语言编写程序」· VHDL 代码 · 共 58 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gepan is
 port( hcnt_in,vcnt_in : in std_logic_vector(9 downto 0);
       clk,vs_in : in std_logic;
       q : out std_logic_vector(2 downto 0));
end entity gepan;
architecture one of gepan is
signal cnt : std_logic;
signal q_x,q_y : std_logic_vector(2 downto 0);
begin
process(clk,vcnt_in)
begin
if clk'event and clk='1' then
 IF vcnt_in<75 THEN q_x<="111";
 ELSIF vcnt_in<150 THEN q_x<="110";
 ELSIF vcnt_in<225 THEN q_x<="101";
 ELSIF vcnt_in<300 THEN q_x<="100";
 ELSIF vcnt_in<375 THEN q_x<="011";
 ELSIF vcnt_in<450 THEN q_x<="010";
 ELSIF vcnt_in<525 THEN q_x<="001";
 ELSE q_x<="000";
 END IF;
end if;
end process;
process(clk,hcnt_in)
begin
if clk'event and clk ='1' then
  if (hcnt_in<100) then q_y<="111";
  elsif (hcnt_in<200) then q_y<="110";
  elsif (hcnt_in<300) then q_y<="101";
  elsif (hcnt_in<400) then q_y<="100";
  elsif (hcnt_in<500) then q_y<="011";
  elsif (hcnt_in<600) then q_y<="010";
  elsif (hcnt_in<700) then q_y<="001";
  else  q_y<="000";
  end if;
end if;
end process;
process(vs_in)
begin
if vs_in'event and vs_in ='0' then
  cnt<= not cnt;
end if;
end process;
process(clk,cnt,q_x,q_y)
begin
if clk'event and clk = '1' then
   if cnt='1' then 
      q<=q_x;
   else q<=q_y;
   end if;
end if;
end process;
end architecture one;