ddc.vhd

verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DDC is
port(
  Clk        : in std_logic;
  Rst        : in std_logic;
  Data_In    : in std_logic_vector(13 downto 0);
  DDC_F      : in std_logic_vector(31 downto 0);    --=X"4A12D773";
  DDC_Data_I : out std_logic_vector(15 downto 0);
  DDC_Data_Q : out std_logic_vector(15 downto 0));
end entity;

architecture Behavioral of DDC is

signal Mul_In    : std_logic_vector(13 downto 0);
signal sin       : std_logic_vector(11 downto 0);
signal cos       : std_logic_vector(11 downto 0);
signal Mul_Cos   : std_logic_vector(13 downto 0);
signal Mul_Sin   : std_logic_vector(13 downto 0);
signal Mulout_En : std_logic;
signal Mulout_I  : std_logic_vector(27 downto 0);
signal Mulout_Q  : std_logic_vector(27 downto 0);
signal En        : std_logic;

component muldown
  port(
    aclr   : in std_logic;
    clock  : in STD_LOGIC ;
    dataa  : in STD_LOGIC_VECTOR (13 downto 0);
    datab  : in STD_LOGIC_VECTOR (13 downto 0);
    result : out STD_LOGIC_VECTOR (27 downto 0));
end component;

component dds1
  port(
    clk      : in STD_LOGIC;
    reset    : in STD_LOGIC;
    fcontrol : in STD_LOGIC_VECTOR(31 downto 0);
    qcosout  : out STD_LOGIC_VECTOR(11 downto 0);
    qsinout  : out STD_LOGIC_VECTOR(11 downto 0));
end component;

begin
En <= '1';

process (Clk, Rst)
begin
  if (Rst='1') then
    Mulout_En <= '0';
    Mul_In    <= "00000000000000";
  elsif (Clk'event and Clk='1') then
    Mul_In    <= Data_In;
    Mulout_En <= En;
  end if;
end process;

dds11 : dds1  
port map(
  clk      => Clk ,
  reset    => Rst ,
  fcontrol => DDC_F ,
  qcosout  => cos ,
  qsinout  => sin);

Mul_Cos <= cos(11)&cos(11)&cos ;
Mul_Sin <= sin(11)&sin(11)&sin ;


Mul_I : muldown 
port map(
  aclr   => Rst,
  clock  => Clk, 
  dataa  => Mul_In,
  datab  => Mul_Cos, 
  result => Mulout_I);

Mul_Q : muldown 
port map(
  aclr   => Rst,
  clock  => Clk, 
  dataa  => Mul_In, 
  datab  => Mul_Sin,
  result => Mulout_Q);		

  DDC_Data_I <= Mulout_I(22 downto 11) & "0000";--最高两位是0
  DDC_Data_Q <= Mulout_Q(22 downto 11) & "0000";

end Behavioral;