hanshu.map.eqn

用FPGA做的DDS函数信号发生器

--GB1L36 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~659
GB1L36 = CARRY(FB1L97 & !FB1L79 & !GB1L34 # !FB1L97 & (!GB1L34 # !FB1L79));


--GB1L37 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~660
GB1L37 = FB1L98 & (GB1L36 $ GND) # !FB1L98 & !GB1L36 & VCC;

--GB1L38 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~661
GB1L38 = CARRY(FB1L98 & !GB1L36);


--GB1L39 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~662
GB1L39 = FB1L99 & !GB1L38 # !FB1L99 & (GB1L38 # GND);

--GB1L40 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~663
GB1L40 = CARRY(!GB1L38 # !FB1L99);


--GB1L41 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~664
GB1L41 = FB1L100 & (GB1L40 $ GND) # !FB1L100 & !GB1L40 & VCC;

--GB1L42 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~665
GB1L42 = CARRY(FB1L100 & !GB1L40);


--GB1L43 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~666
GB1L43 = FB1L101 & !GB1L42 # !FB1L101 & (GB1L42 # GND);

--GB1L44 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~667
GB1L44 = CARRY(!GB1L42 # !FB1L101);


--GB1L45 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~668
GB1L45 = FB1L102 & (GB1L44 $ GND) # !FB1L102 & !GB1L44 & VCC;

--GB1L46 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~669
GB1L46 = CARRY(FB1L102 & !GB1L44);


--GB1L47 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~670
GB1L47 = FB1L103 $ GB1L46;


--MC1L1 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~594
MC1L1 = GB1L3 & (GB1L1 $ VCC) # !GB1L3 & GB1L1 & VCC;

--MC1L2 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~595
MC1L2 = CARRY(GB1L3 & GB1L1);


--MC1L3 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~596
MC1L3 = GB1L5 & !MC1L2 # !GB1L5 & (MC1L2 # GND);

--MC1L4 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~597
MC1L4 = CARRY(!MC1L2 # !GB1L5);


--MC1L5 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~598
MC1L5 = GB1L7 & (MC1L4 $ GND) # !GB1L7 & !MC1L4 & VCC;

--MC1L6 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~599
MC1L6 = CARRY(GB1L7 & !MC1L4);


--MC1L7 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~600
MC1L7 = GB1L9 & !MC1L6 # !GB1L9 & (MC1L6 # GND);

--MC1L8 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~601
MC1L8 = CARRY(!MC1L6 # !GB1L9);


--MC1L9 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~602
MC1L9 = GB1L11 & (MC1L8 $ GND) # !GB1L11 & !MC1L8 & VCC;

--MC1L10 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~603
MC1L10 = CARRY(GB1L11 & !MC1L8);


--MC1L11 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~604
MC1L11 = GB1L13 & !MC1L10 # !GB1L13 & (MC1L10 # GND);

--MC1L12 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~605
MC1L12 = CARRY(!MC1L10 # !GB1L13);


--MC1L13 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~606
MC1L13 = GB1L15 & (MC1L12 $ GND) # !GB1L15 & !MC1L12 & VCC;

--MC1L14 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~607
MC1L14 = CARRY(GB1L15 & !MC1L12);


--MC1L15 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~608
MC1L15 = GB1L17 & !MC1L14 # !GB1L17 & (MC1L14 # GND);

--MC1L16 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~609
MC1L16 = CARRY(!MC1L14 # !GB1L17);


--MC1L17 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~610
MC1L17 = GB1L19 & (MC1L16 $ GND) # !GB1L19 & !MC1L16 & VCC;

--MC1L18 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~611
MC1L18 = CARRY(GB1L19 & !MC1L16);


--MC1L19 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~612
MC1L19 = GB1L21 & !MC1L18 # !GB1L21 & (MC1L18 # GND);

--MC1L20 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~613
MC1L20 = CARRY(!MC1L18 # !GB1L21);


--MC1L21 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~614
MC1L21 = GB1L23 & (MC1L20 $ GND) # !GB1L23 & !MC1L20 & VCC;

--MC1L22 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~615
MC1L22 = CARRY(GB1L23 & !MC1L20);


--MC1L23 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~616
MC1L23 = GB1L25 & !MC1L22 # !GB1L25 & (MC1L22 # GND);

--MC1L24 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~617
MC1L24 = CARRY(!MC1L22 # !GB1L25);


--MC1L25 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~618
MC1L25 = GB1L27 & (MC1L24 $ GND) # !GB1L27 & !MC1L24 & VCC;

--MC1L26 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~619
MC1L26 = CARRY(GB1L27 & !MC1L24);


--MC1L27 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~620
MC1L27 = GB1L29 & !MC1L26 # !GB1L29 & (MC1L26 # GND);

--MC1L28 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~621
MC1L28 = CARRY(!MC1L26 # !GB1L29);


--MC1L29 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~622
MC1L29 = GB1L31 & (MC1L28 $ GND) # !GB1L31 & !MC1L28 & VCC;

--MC1L30 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~623
MC1L30 = CARRY(GB1L31 & !MC1L28);


--MC1L31 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~624
MC1L31 = GB1L33 & !MC1L30 # !GB1L33 & (MC1L30 # GND);

--MC1L32 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~625
MC1L32 = CARRY(!MC1L30 # !GB1L33);


--MC1L33 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~626
MC1L33 = GB1L35 & (MC1L32 $ GND) # !GB1L35 & !MC1L32 & VCC;

--MC1L34 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~627
MC1L34 = CARRY(GB1L35 & !MC1L32);


--MC1L35 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~628
MC1L35 = GB1L37 & !MC1L34 # !GB1L37 & (MC1L34 # GND);

--MC1L36 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~629
MC1L36 = CARRY(!MC1L34 # !GB1L37);


--MC1L37 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~630
MC1L37 = GB1L39 & (MC1L36 $ GND) # !GB1L39 & !MC1L36 & VCC;

--MC1L38 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~631
MC1L38 = CARRY(GB1L39 & !MC1L36);


--MC1L39 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~632
MC1L39 = GB1L41 & !MC1L38 # !GB1L41 & (MC1L38 # GND);

--MC1L40 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~633
MC1L40 = CARRY(!MC1L38 # !GB1L41);


--MC1L41 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~634
MC1L41 = GB1L43 & (MC1L40 $ GND) # !GB1L43 & !MC1L40 & VCC;

--MC1L42 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~635
MC1L42 = CARRY(GB1L43 & !MC1L40);


--MC1L43 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~636
MC1L43 = GB1L45 & !MC1L42 # !GB1L45 & (MC1L42 # GND);

--MC1L44 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~637
MC1L44 = CARRY(!MC1L42 # !GB1L45);


--MC1L45 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~638
MC1L45 = GB1L47 & (MC1L44 $ GND) # !GB1L47 & !MC1L44 & VCC;

--MC1L46 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~639
MC1L46 = CARRY(GB1L47 & !MC1L44);


--MC1L47 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~640
MC1L47 = MC1L46;


--MB1L24 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|StageOut[598]~43061
MB1L24 = MC1L47 & MC1L45 # !MC1L47 & (GB1L47);


--MB1L23 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|StageOut[597]~43062
MB1L23 = MC1L47 & MC1L43 # !MC1L47 & (GB1L45);


--MB1L22 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|StageOut[596]~43063
MB1L22 = MC1L47 & MC1L41 # !MC1L47 & (GB1L43);


--MB1L21 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|StageOut[595]~43064
MB1L21 = MC1L47 & MC1L39 # !MC1L47 & (GB1L41);