hanshu.map.eqn

用FPGA做的DDS函数信号发生器

--FB1_w26w[2] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[2]
FB1_w26w[2] = FB1L3;

--FB1_w26w[3] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[3]
FB1_w26w[3] = FB1L4;

--FB1_w26w[4] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[4]
FB1_w26w[4] = FB1L5;

--FB1_w26w[5] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[5]
FB1_w26w[5] = FB1L6;

--FB1_w26w[6] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[6]
FB1_w26w[6] = FB1L7;

--FB1_w26w[7] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[7]
FB1_w26w[7] = FB1L8;

--FB1_w26w[8] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[8]
FB1_w26w[8] = FB1L9;

--FB1_w26w[9] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[9]
FB1_w26w[9] = FB1L10;

--FB1_w26w[10] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[10]
FB1_w26w[10] = FB1L11;

--FB1_w26w[11] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[11]
FB1_w26w[11] = FB1L12;

--FB1_w26w[12] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[12]
FB1_w26w[12] = FB1L13;

--FB1_w26w[13] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[13]
FB1_w26w[13] = FB1L14;

--FB1_w26w[14] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[14]
FB1_w26w[14] = FB1L15;

--FB1_w26w[15] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[15]
FB1_w26w[15] = FB1L16;

--FB1_w26w[16] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[16]
FB1_w26w[16] = FB1L17;

--FB1_w26w[17] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[17]
FB1_w26w[17] = FB1L18;

--FB1L62 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT18
FB1L62 = FB1L19;

--FB1L63 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT19
FB1L63 = FB1L20;

--FB1L64 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT20
FB1L64 = FB1L21;

--FB1L65 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT21
FB1L65 = FB1L22;

--FB1L66 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT22
FB1L66 = FB1L23;

--FB1L67 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT23
FB1L67 = FB1L24;

--FB1L68 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT24
FB1L68 = FB1L25;

--FB1L69 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT25
FB1L69 = FB1L26;

--FB1L70 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT26
FB1L70 = FB1L27;

--FB1L71 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT27
FB1L71 = FB1L28;

--FB1L72 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT28
FB1L72 = FB1L29;

--FB1L73 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT29
FB1L73 = FB1L30;

--FB1L74 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT30
FB1L74 = FB1L31;

--FB1L75 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT31
FB1L75 = FB1L32;

--FB1L76 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT32
FB1L76 = FB1L33;

--FB1L77 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT33
FB1L77 = FB1L34;

--FB1L78 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT34
FB1L78 = FB1L35;

--FB1L79 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out2~DATAOUT35
FB1L79 = FB1L36;


--GB1L1 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~624
GB1L1 = FB1_mac_out4 & (FB1L62 $ VCC) # !FB1_mac_out4 & FB1L62 & VCC;

--GB1L2 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~625
GB1L2 = CARRY(FB1_mac_out4 & FB1L62);


--GB1L3 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~626
GB1L3 = FB1L81 & (FB1L63 & GB1L2 & VCC # !FB1L63 & !GB1L2) # !FB1L81 & (FB1L63 & !GB1L2 # !FB1L63 & (GB1L2 # GND));

--GB1L4 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~627
GB1L4 = CARRY(FB1L81 & !FB1L63 & !GB1L2 # !FB1L81 & (!GB1L2 # !FB1L63));


--GB1L5 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~628
GB1L5 = (FB1L82 $ FB1L64 $ !GB1L4) # GND;

--GB1L6 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~629
GB1L6 = CARRY(FB1L82 & (FB1L64 # !GB1L4) # !FB1L82 & FB1L64 & !GB1L4);


--GB1L7 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~630
GB1L7 = FB1L83 & (FB1L65 & GB1L6 & VCC # !FB1L65 & !GB1L6) # !FB1L83 & (FB1L65 & !GB1L6 # !FB1L65 & (GB1L6 # GND));

--GB1L8 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~631
GB1L8 = CARRY(FB1L83 & !FB1L65 & !GB1L6 # !FB1L83 & (!GB1L6 # !FB1L65));


--GB1L9 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~632
GB1L9 = (FB1L84 $ FB1L66 $ !GB1L8) # GND;

--GB1L10 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~633
GB1L10 = CARRY(FB1L84 & (FB1L66 # !GB1L8) # !FB1L84 & FB1L66 & !GB1L8);


--GB1L11 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~634
GB1L11 = FB1L85 & (FB1L67 & GB1L10 & VCC # !FB1L67 & !GB1L10) # !FB1L85 & (FB1L67 & !GB1L10 # !FB1L67 & (GB1L10 # GND));

--GB1L12 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~635
GB1L12 = CARRY(FB1L85 & !FB1L67 & !GB1L10 # !FB1L85 & (!GB1L10 # !FB1L67));


--GB1L13 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~636
GB1L13 = (FB1L86 $ FB1L68 $ !GB1L12) # GND;

--GB1L14 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~637
GB1L14 = CARRY(FB1L86 & (FB1L68 # !GB1L12) # !FB1L86 & FB1L68 & !GB1L12);


--GB1L15 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~638
GB1L15 = FB1L87 & (FB1L69 & GB1L14 & VCC # !FB1L69 & !GB1L14) # !FB1L87 & (FB1L69 & !GB1L14 # !FB1L69 & (GB1L14 # GND));

--GB1L16 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~639
GB1L16 = CARRY(FB1L87 & !FB1L69 & !GB1L14 # !FB1L87 & (!GB1L14 # !FB1L69));


--GB1L17 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~640
GB1L17 = (FB1L88 $ FB1L70 $ !GB1L16) # GND;

--GB1L18 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~641
GB1L18 = CARRY(FB1L88 & (FB1L70 # !GB1L16) # !FB1L88 & FB1L70 & !GB1L16);


--GB1L19 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~642
GB1L19 = FB1L89 & (FB1L71 & GB1L18 & VCC # !FB1L71 & !GB1L18) # !FB1L89 & (FB1L71 & !GB1L18 # !FB1L71 & (GB1L18 # GND));

--GB1L20 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~643
GB1L20 = CARRY(FB1L89 & !FB1L71 & !GB1L18 # !FB1L89 & (!GB1L18 # !FB1L71));


--GB1L21 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~644
GB1L21 = (FB1L90 $ FB1L72 $ !GB1L20) # GND;

--GB1L22 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~645
GB1L22 = CARRY(FB1L90 & (FB1L72 # !GB1L20) # !FB1L90 & FB1L72 & !GB1L20);


--GB1L23 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~646
GB1L23 = FB1L91 & (FB1L73 & GB1L22 & VCC # !FB1L73 & !GB1L22) # !FB1L91 & (FB1L73 & !GB1L22 # !FB1L73 & (GB1L22 # GND));

--GB1L24 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~647
GB1L24 = CARRY(FB1L91 & !FB1L73 & !GB1L22 # !FB1L91 & (!GB1L22 # !FB1L73));


--GB1L25 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~648
GB1L25 = (FB1L92 $ FB1L74 $ !GB1L24) # GND;

--GB1L26 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~649
GB1L26 = CARRY(FB1L92 & (FB1L74 # !GB1L24) # !FB1L92 & FB1L74 & !GB1L24);


--GB1L27 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~650
GB1L27 = FB1L93 & (FB1L75 & GB1L26 & VCC # !FB1L75 & !GB1L26) # !FB1L93 & (FB1L75 & !GB1L26 # !FB1L75 & (GB1L26 # GND));

--GB1L28 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~651
GB1L28 = CARRY(FB1L93 & !FB1L75 & !GB1L26 # !FB1L93 & (!GB1L26 # !FB1L75));


--GB1L29 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~652
GB1L29 = (FB1L94 $ FB1L76 $ !GB1L28) # GND;

--GB1L30 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~653
GB1L30 = CARRY(FB1L94 & (FB1L76 # !GB1L28) # !FB1L94 & FB1L76 & !GB1L28);


--GB1L31 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~654
GB1L31 = FB1L95 & (FB1L77 & GB1L30 & VCC # !FB1L77 & !GB1L30) # !FB1L95 & (FB1L77 & !GB1L30 # !FB1L77 & (GB1L30 # GND));

--GB1L32 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~655
GB1L32 = CARRY(FB1L95 & !FB1L77 & !GB1L30 # !FB1L95 & (!GB1L30 # !FB1L77));


--GB1L33 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~656
GB1L33 = (FB1L96 $ FB1L78 $ !GB1L32) # GND;

--GB1L34 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~657
GB1L34 = CARRY(FB1L96 & (FB1L78 # !GB1L32) # !FB1L96 & FB1L78 & !GB1L32);


--GB1L35 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~658
GB1L35 = FB1L97 & (FB1L79 & GB1L34 & VCC # !FB1L79 & !GB1L34) # !FB1L97 & (FB1L79 & !GB1L34 # !FB1L79 & (GB1L34 # GND));