hanshu.map.eqn

用FPGA做的DDS函数信号发生器

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--DB1_q_a[9] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[9]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[9]_PORT_A_address_reg = DFFE(DB1_q_a[9]_PORT_A_address, DB1_q_a[9]_clock_0, , , );
DB1_q_a[9]_clock_0 = clk;
DB1_q_a[9]_PORT_A_data_out = MEMORY(, , DB1_q_a[9]_PORT_A_address_reg, , , , , , DB1_q_a[9]_clock_0, , , , , );
DB1_q_a[9]_PORT_A_data_out_reg = DFFE(DB1_q_a[9]_PORT_A_data_out, DB1_q_a[9]_clock_0, , , );
DB1_q_a[9] = DB1_q_a[9]_PORT_A_data_out_reg[0];


--DB1_q_a[8] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[8]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[8]_PORT_A_address_reg = DFFE(DB1_q_a[8]_PORT_A_address, DB1_q_a[8]_clock_0, , , );
DB1_q_a[8]_clock_0 = clk;
DB1_q_a[8]_PORT_A_data_out = MEMORY(, , DB1_q_a[8]_PORT_A_address_reg, , , , , , DB1_q_a[8]_clock_0, , , , , );
DB1_q_a[8]_PORT_A_data_out_reg = DFFE(DB1_q_a[8]_PORT_A_data_out, DB1_q_a[8]_clock_0, , , );
DB1_q_a[8] = DB1_q_a[8]_PORT_A_data_out_reg[0];


--DB1_q_a[7] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[7]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[7]_PORT_A_address_reg = DFFE(DB1_q_a[7]_PORT_A_address, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7]_clock_0 = clk;
DB1_q_a[7]_PORT_A_data_out = MEMORY(, , DB1_q_a[7]_PORT_A_address_reg, , , , , , DB1_q_a[7]_clock_0, , , , , );
DB1_q_a[7]_PORT_A_data_out_reg = DFFE(DB1_q_a[7]_PORT_A_data_out, DB1_q_a[7]_clock_0, , , );
DB1_q_a[7] = DB1_q_a[7]_PORT_A_data_out_reg[0];


--DB1_q_a[6] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[6]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[6]_PORT_A_address_reg = DFFE(DB1_q_a[6]_PORT_A_address, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6]_clock_0 = clk;
DB1_q_a[6]_PORT_A_data_out = MEMORY(, , DB1_q_a[6]_PORT_A_address_reg, , , , , , DB1_q_a[6]_clock_0, , , , , );
DB1_q_a[6]_PORT_A_data_out_reg = DFFE(DB1_q_a[6]_PORT_A_data_out, DB1_q_a[6]_clock_0, , , );
DB1_q_a[6] = DB1_q_a[6]_PORT_A_data_out_reg[0];


--DB1_q_a[5] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[5]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[5]_PORT_A_address_reg = DFFE(DB1_q_a[5]_PORT_A_address, DB1_q_a[5]_clock_0, , , );
DB1_q_a[5]_clock_0 = clk;
DB1_q_a[5]_PORT_A_data_out = MEMORY(, , DB1_q_a[5]_PORT_A_address_reg, , , , , , DB1_q_a[5]_clock_0, , , , , );
DB1_q_a[5]_PORT_A_data_out_reg = DFFE(DB1_q_a[5]_PORT_A_data_out, DB1_q_a[5]_clock_0, , , );
DB1_q_a[5] = DB1_q_a[5]_PORT_A_data_out_reg[0];


--DB1_q_a[4] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[4]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[4]_PORT_A_address_reg = DFFE(DB1_q_a[4]_PORT_A_address, DB1_q_a[4]_clock_0, , , );
DB1_q_a[4]_clock_0 = clk;
DB1_q_a[4]_PORT_A_data_out = MEMORY(, , DB1_q_a[4]_PORT_A_address_reg, , , , , , DB1_q_a[4]_clock_0, , , , , );
DB1_q_a[4]_PORT_A_data_out_reg = DFFE(DB1_q_a[4]_PORT_A_data_out, DB1_q_a[4]_clock_0, , , );
DB1_q_a[4] = DB1_q_a[4]_PORT_A_data_out_reg[0];


--DB1_q_a[3] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[3]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[3]_PORT_A_address_reg = DFFE(DB1_q_a[3]_PORT_A_address, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3]_clock_0 = clk;
DB1_q_a[3]_PORT_A_data_out = MEMORY(, , DB1_q_a[3]_PORT_A_address_reg, , , , , , DB1_q_a[3]_clock_0, , , , , );
DB1_q_a[3]_PORT_A_data_out_reg = DFFE(DB1_q_a[3]_PORT_A_data_out, DB1_q_a[3]_clock_0, , , );
DB1_q_a[3] = DB1_q_a[3]_PORT_A_data_out_reg[0];


--DB1_q_a[2] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[2]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[2]_PORT_A_address_reg = DFFE(DB1_q_a[2]_PORT_A_address, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2]_clock_0 = clk;
DB1_q_a[2]_PORT_A_data_out = MEMORY(, , DB1_q_a[2]_PORT_A_address_reg, , , , , , DB1_q_a[2]_clock_0, , , , , );
DB1_q_a[2]_PORT_A_data_out_reg = DFFE(DB1_q_a[2]_PORT_A_data_out, DB1_q_a[2]_clock_0, , , );
DB1_q_a[2] = DB1_q_a[2]_PORT_A_data_out_reg[0];


--DB1_q_a[1] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[1]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[1]_PORT_A_address_reg = DFFE(DB1_q_a[1]_PORT_A_address, DB1_q_a[1]_clock_0, , , );
DB1_q_a[1]_clock_0 = clk;
DB1_q_a[1]_PORT_A_data_out = MEMORY(, , DB1_q_a[1]_PORT_A_address_reg, , , , , , DB1_q_a[1]_clock_0, , , , , );
DB1_q_a[1]_PORT_A_data_out_reg = DFFE(DB1_q_a[1]_PORT_A_data_out, DB1_q_a[1]_clock_0, , , );
DB1_q_a[1] = DB1_q_a[1]_PORT_A_data_out_reg[0];


--DB1_q_a[0] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = clk;
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0] = DB1_q_a[0]_PORT_A_data_out_reg[0];


--FB1_mac_out4 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4
--DSP Block Operation Mode: Simple Multiplier (18-bit)
FB1_mac_out4 = FB1_mac_mult3;

--FB1L81 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT1
FB1L81 = FB1L38;

--FB1L82 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT2
FB1L82 = FB1L39;

--FB1L83 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT3
FB1L83 = FB1L40;

--FB1L84 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT4
FB1L84 = FB1L41;

--FB1L85 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT5
FB1L85 = FB1L42;

--FB1L86 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT6
FB1L86 = FB1L43;

--FB1L87 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT7
FB1L87 = FB1L44;

--FB1L88 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT8
FB1L88 = FB1L45;

--FB1L89 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT9
FB1L89 = FB1L46;

--FB1L90 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT10
FB1L90 = FB1L47;

--FB1L91 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT11
FB1L91 = FB1L48;

--FB1L92 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT12
FB1L92 = FB1L49;

--FB1L93 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT13
FB1L93 = FB1L50;

--FB1L94 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT14
FB1L94 = FB1L51;

--FB1L95 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT15
FB1L95 = FB1L52;

--FB1L96 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT16
FB1L96 = FB1L53;

--FB1L97 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT17
FB1L97 = FB1L54;

--FB1L98 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT18
FB1L98 = FB1L55;

--FB1L99 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT19
FB1L99 = FB1L56;

--FB1L100 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT20
FB1L100 = FB1L57;

--FB1L101 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT21
FB1L101 = FB1L58;

--FB1L102 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT22
FB1L102 = FB1L59;

--FB1L103 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT23
FB1L103 = FB1L60;


--FB1_w26w[0] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[0]
--DSP Block Operation Mode: Simple Multiplier (18-bit)
FB1_w26w[0] = FB1_mac_mult1;

--FB1_w26w[1] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[1]
FB1_w26w[1] = FB1L2;