hanshu.hif

用FPGA做的DDS函数信号发生器

Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
10
705
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
fangzhen
# storage
db|hanshu.(0).cnf
db|hanshu.(0).cnf
# case_insensitive
# source_file
fangzhen.bdf
6dbd392af43a61e7f2f4c4963bb2d3
23
# end
# entity
ADDER4B
# storage
db|hanshu.(1).cnf
db|hanshu.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
adder4b.vhd
60326b7d279fa056d083cee37215bd8
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
ADDER4B:inst11
}
# end
# entity
M
# storage
db|hanshu.(2).cnf
db|hanshu.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
m.vhd
34cc2b6bbff0eb77657429c17312a17
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
M:inst
}
# end
# entity
altsyncram
# storage
db|hanshu.(5).cnf
db|hanshu.(5).cnf
# case_insensitive
# source_file
d:|altera|quartus51|libraries|megafunctions|altsyncram.tdf
6d23188b861aaf86e7848b32051ebea
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
sin.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_pov
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
d:|altera|quartus51|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|altera|quartus51|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
d:|altera|quartus51|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
d:|altera|quartus51|libraries|megafunctions|aglobal51.inc
c49d61e8168d42962ec885e3e17640c2
d:|altera|quartus51|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
d:|altera|quartus51|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
d:|altera|quartus51|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
d:|altera|quartus51|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
d:|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|altera|quartus51|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
sM:inst5|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_pov
# storage
db|hanshu.(6).cnf
db|hanshu.(6).cnf
# case_insensitive
# source_file
db|altsyncram_pov.tdf
7c3c80e4dbdeba7c7845112e46fae4a6
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sin.mif
99bae60e6d66c1406a84c7664c77
}
# hierarchies {
sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated
}
# end
# entity
JIA
# storage
db|hanshu.(8).cnf
db|hanshu.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
JIA.vhd
24fdc4739156796d87e74f4ac8481c17
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
JIA:inst3
}
# end
# entity
lpm_add_sub
# storage
db|hanshu.(9).cnf
db|hanshu.(9).cnf
# case_insensitive
# source_file
d:|altera|quartus51|libraries|megafunctions|lpm_add_sub.tdf
63e31d31a69d292a0b55c3794c42e38
6
# user_parameter {
LPM_WIDTH
24
PARAMETER_DEC
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_pmg
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
}
# include_file {
d:|altera|quartus51|libraries|megafunctions|aglobal51.inc
c49d61e8168d42962ec885e3e17640c2
d:|altera|quartus51|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
d:|altera|quartus51|libraries|megafunctions|look_add.inc
ab9f577d30c5ef3166fab6c1c32c4a
d:|altera|quartus51|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
d:|altera|quartus51|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
d:|altera|quartus51|libraries|megafunctions|alt_stratix_add_sub.inc
c08f604aefba5b4f1f554e565113c6
d:|altera|quartus51|libraries|megafunctions|alt_mercury_add_sub.inc
ae39f15ed67cc9a095d29f68f6ad0f8
}
# hierarchies {
JIA:inst3|lpm_add_sub:lpm_add_sub_component
}
# end
# entity
add_sub_pmg
# storage
db|hanshu.(10).cnf
db|hanshu.(10).cnf
# case_insensitive
# source_file
db|add_sub_pmg.tdf
4cd05327e24ba7de6bb5686a944b29a
6
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
}
# hierarchies {
JIA:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_pmg:auto_generated
}
# end
# entity
chuan
# storage
db|hanshu.(11).cnf
db|hanshu.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
chuan.vhd
ee34d9f811a28de8c6585ca3811aae16
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
chuan:inst2
}
# end
# entity
last
# storage
db|hanshu.(12).cnf
db|hanshu.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
last.vhd
e61864b7fc853a9b803c946e96e51
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
last:inst1
}
# end
# entity
last1
# storage
db|hanshu.(13).cnf
db|hanshu.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
last1.vhd
d6523f711b9ce335f0ecd9697735b86
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
last1:inst9
}
# end
# entity
lpm_divide0
# storage
db|hanshu.(14).cnf
db|hanshu.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_divide0.vhd
5a214b4487e56b6257130f3fd3b7780
4
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lpm_divide0:inst8
}
# end
# entity
lpm_divide
# storage
db|hanshu.(15).cnf
db|hanshu.(15).cnf
# case_insensitive
# source_file
d:|altera|quartus51|libraries|megafunctions|lpm_divide.tdf
22636caca03f2256c835a4b69da4cd
6
# user_parameter {
LPM_WIDTHN
42
PARAMETER_DEC
USR
LPM_WIDTHD
24
PARAMETER_DEC
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_lej
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
remain9
-1
3
remain8
-1
3
remain7
-1
3
remain6
-1
3
remain5
-1
3
remain4
-1
3
remain3
-1
3
remain23
-1
3
remain22
-1
3
remain21
-1
3
remain20
-1
3
remain2
-1
3
remain19
-1
3
remain18
-1
3
remain17
-1
3
remain16
-1
3
remain15
-1
3
remain14
-1
3
remain13
-1
3
remain12
-1
3
remain11
-1
3
remain10
-1
3
remain1
-1
3
remain0
-1
3
quotient9
-1
3
quotient8
-1
3
quotient7
-1
3
quotient6
-1
3
quotient5
-1
3
quotient41
-1
3
quotient40
-1
3
quotient4
-1
3
quotient39
-1
3
quotient38
-1
3
quotient37
-1
3
quotient36
-1
3
quotient35
-1
3
quotient34
-1
3
quotient33
-1
3
quotient32
-1
3
quotient31
-1
3
quotient30
-1
3
quotient3
-1
3
quotient29
-1
3
quotient28
-1
3
quotient27
-1
3
quotient26
-1
3
quotient25
-1
3
quotient24
-1
3
quotient23
-1
3
quotient22
-1
3
quotient21
-1
3
quotient20
-1
3
quotient2