alt_u_div_53e.tdf

用FPGA做的DDS函数信号发生器

--synthesis_resources = 
SUBDESIGN alt_u_div_53e
( 
	den_out[13..0]	:	output;
	denominator[13..0]	:	input;
	numerator[16..0]	:	input;
	quotient[16..0]	:	output;
	remainder[13..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_6m8;
	add_sub_1 : add_sub_7m8;
	add_sub_10 : add_sub_nn8;
	add_sub_11 : add_sub_on8;
	add_sub_12 : add_sub_pn8;
	add_sub_13 : add_sub_qn8;
	add_sub_14 : add_sub_rn8;
	add_sub_15 : add_sub_rn8;
	add_sub_16 : add_sub_rn8;
	add_sub_2 : add_sub_8m8;
	add_sub_3 : add_sub_9m8;
	add_sub_4 : add_sub_am8;
	add_sub_5 : add_sub_bm8;
	add_sub_6 : add_sub_cm8;
	add_sub_7 : add_sub_dm8;
	add_sub_8 : add_sub_em8;
	add_sub_9 : add_sub_mn8;
	DenominatorIn[269..0]	: WIRE;
	DenominatorIn_tmp[269..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[305..0]	: WIRE;
	NumeratorIn[305..0]	: WIRE;
	NumeratorIn_tmp[305..0]	: WIRE;
	prestg[254..0]	: WIRE;
	quotient_tmp[16..0]	: WIRE;
	sel[251..0]	: WIRE;
	selnose[305..0]	: WIRE;
	StageIn[269..0]	: WIRE;
	StageIn_tmp[269..0]	: WIRE;
	StageOut[254..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[16..16];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[15..15], NumeratorIn[32..32]);
	add_sub_1.datab[1..0] = DenominatorIn[16..15];
	add_sub_10.dataa[] = ( StageIn[159..150], NumeratorIn[176..176]);
	add_sub_10.datab[10..0] = DenominatorIn[160..150];