lpm_divide_1dj.tdf

用FPGA做的DDS函数信号发生器

--lpm_divide DEVICE_FAMILY="Cyclone II" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_REMAINDERPOSITIVE="TRUE" LPM_WIDTHD=7 LPM_WIDTHN=10 OPTIMIZE_FOR_SPEED=5 denom numer quotient remain
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_abs 2005:08:16:22:24:32:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_divide 2005:03:24:00:40:32:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ  VERSION_END


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FUNCTION sign_div_unsign_2jg (denominator[6..0], numerator[9..0])
RETURNS ( quotient[9..0], remainder[6..0]);

--synthesis_resources = lut 8 
SUBDESIGN lpm_divide_1dj
( 
	denom[6..0]	:	input;
	numer[9..0]	:	input;
	quotient[9..0]	:	output;
	remain[6..0]	:	output;
) 
VARIABLE 
	divider : sign_div_unsign_2jg;
	numer_tmp[9..0]	: WIRE;

BEGIN 
	divider.denominator[] = denom[];
	divider.numerator[] = numer_tmp[];
	numer_tmp[] = numer[];
	quotient[] = divider.quotient[];
	remain[] = divider.remainder[];
END;
--VALID FILE