mult_o0r.tdf

用FPGA做的DDS函数信号发生器

--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" DSP_BLOCK_BALANCING="Auto" INPUT_B_IS_CONSTANT="YES" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=18 LPM_WIDTHB=24 LPM_WIDTHP=42 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_mult 2006:01:05:15:20:18:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_padd 2006:01:13:16:04:50:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cycloneii_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb)
WITH ( 	dataa_clock,	dataa_width,	datab_clock,	datab_width,	signa_clock,	signb_clock) 
RETURNS ( dataout[dataa_width+datab_width-1..0]);
PARAMETERS
(
	dataa_width = 0
);
FUNCTION cycloneii_mac_out (aclr, clk, dataa[dataa_width-1..0], ena)
WITH ( 	dataa_width,	output_clock) 
RETURNS ( dataout[dataa_width-1..0]);
FUNCTION add_sub_37h (dataa[24..0], datab[24..0])
RETURNS ( result[24..0]);

--synthesis_resources = dsp_9bit 4 lut 25 
SUBDESIGN mult_o0r
( 
	dataa[17..0]	:	input;
	datab[23..0]	:	input;
	result[41..0]	:	output;
) 
VARIABLE 
	mac_mult1 : cycloneii_mac_mult
		WITH (
			dataa_clock = "none",
			dataa_width = 18,
			datab_clock = "none",
			datab_width = 18,
			signa_clock = "none",
			signb_clock = "none"
		);
	mac_mult3 : cycloneii_mac_mult
		WITH (
			dataa_clock = "none",
			dataa_width = 18,
			datab_clock = "none",
			datab_width = 6,
			signa_clock = "none",
			signb_clock = "none"
		);
	mac_out2 : cycloneii_mac_out
		WITH (
			dataa_width = 36,
			output_clock = "none"
		);
	mac_out4 : cycloneii_mac_out
		WITH (
			dataa_width = 24,
			output_clock = "none"
		);
	add_sub5 : add_sub_37h;
	w26w[42..0]	: WIRE;

BEGIN 
	mac_mult1.dataa[] = ( dataa[17..0]);
	mac_mult1.datab[] = ( datab[17..0]);
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_mult3.dataa[] = ( dataa[17..0]);
	mac_mult3.datab[] = ( datab[23..18]);
	mac_mult3.signa = B"0";
	mac_mult3.signb = B"0";
	mac_out2.dataa[] = mac_mult1.dataout[];
	mac_out4.dataa[] = mac_mult3.dataout[];
	add_sub5.dataa[] = ( B"0000000", mac_out2.dataout[35..18]);
	add_sub5.datab[] = ( B"0", mac_out4.dataout[23..0]);
	result[41..0] = w26w[41..0];
	w26w[] = ( add_sub5.result[], mac_out2.dataout[17..0]);
END;
--VALID FILE