adder4b.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER4B IS
PORT(cp,r:in std_logic;
     A18: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
     B18: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
     S18: buffer STD_LOGIC_VECTOR(17 DOWNTO 0);
     CO19:buffer STD_LOGIC);
END ADDER4B;
ARCHITECTURE ART OF ADDER4B IS
   SIGNAL A19,B19:STD_LOGIC_VECTOR(18 DOWNTO 0);
   SIGNAL S19:STD_LOGIC_VECTOR(18 DOWNTO 0);
    BEGIN 
     A19<='0' & A18;
     B19<='0' & B18;
 PROCESS (cp,A18,B18)
   begin
   if r='0' then
      if cp'event and cp='1' then 
      --A19<='0' & A18;
      --B19<='0' & B18;
         S19<=A19+B19;
       END IF;
   elsif r='1' then 
      s19<="0000000000000000000";
    end if;
     s18<=S19(17 DOWNTO 0);
     CO19<=S19(18);
   end process; 
END ARCHITECTURE ART;