hanshu.fit.eqn

用FPGA做的DDS函数信号发生器

--GB1L37 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~660 at LCCOMB_X15_Y5_N12
GB1L37 = FB1L122 & (GB1L36 $ GND) # !FB1L122 & !GB1L36 & VCC;

--GB1L38 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~661 at LCCOMB_X15_Y5_N12
GB1L38 = CARRY(FB1L122 & !GB1L36);


--GB1L39 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~662 at LCCOMB_X15_Y5_N14
GB1L39 = FB1L123 & !GB1L38 # !FB1L123 & (GB1L38 # GND);

--GB1L40 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~663 at LCCOMB_X15_Y5_N14
GB1L40 = CARRY(!GB1L38 # !FB1L123);


--GB1L41 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~664 at LCCOMB_X15_Y5_N16
GB1L41 = FB1L124 & (GB1L40 $ GND) # !FB1L124 & !GB1L40 & VCC;

--GB1L42 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~665 at LCCOMB_X15_Y5_N16
GB1L42 = CARRY(FB1L124 & !GB1L40);


--GB1L43 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~666 at LCCOMB_X15_Y5_N18
GB1L43 = FB1L125 & !GB1L42 # !FB1L125 & (GB1L42 # GND);

--GB1L44 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~667 at LCCOMB_X15_Y5_N18
GB1L44 = CARRY(!GB1L42 # !FB1L125);


--GB1L45 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~668 at LCCOMB_X15_Y5_N20
GB1L45 = FB1L126 & (GB1L44 $ GND) # !FB1L126 & !GB1L44 & VCC;

--GB1L46 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~669 at LCCOMB_X15_Y5_N20
GB1L46 = CARRY(FB1L126 & !GB1L44);


--GB1L47 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|add_sub_37h:add_sub5|add_sub_cella[0]~670 at LCCOMB_X15_Y5_N22
GB1L47 = GB1L46 $ FB1L127;


--MC1L1 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~594 at LCCOMB_X17_Y5_N8
MC1L1 = GB1L3 & (GB1L1 $ VCC) # !GB1L3 & GB1L1 & VCC;

--MC1L2 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~595 at LCCOMB_X17_Y5_N8
MC1L2 = CARRY(GB1L3 & GB1L1);


--MC1L3 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~596 at LCCOMB_X17_Y5_N10
MC1L3 = GB1L5 & !MC1L2 # !GB1L5 & (MC1L2 # GND);

--MC1L4 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~597 at LCCOMB_X17_Y5_N10
MC1L4 = CARRY(!MC1L2 # !GB1L5);


--MC1L5 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~598 at LCCOMB_X17_Y5_N12
MC1L5 = GB1L7 & (MC1L4 $ GND) # !GB1L7 & !MC1L4 & VCC;

--MC1L6 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~599 at LCCOMB_X17_Y5_N12
MC1L6 = CARRY(GB1L7 & !MC1L4);


--MC1L7 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~600 at LCCOMB_X17_Y5_N14
MC1L7 = GB1L9 & !MC1L6 # !GB1L9 & (MC1L6 # GND);

--MC1L8 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~601 at LCCOMB_X17_Y5_N14
MC1L8 = CARRY(!MC1L6 # !GB1L9);


--MC1L9 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~602 at LCCOMB_X17_Y5_N16
MC1L9 = GB1L11 & (MC1L8 $ GND) # !GB1L11 & !MC1L8 & VCC;

--MC1L10 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~603 at LCCOMB_X17_Y5_N16
MC1L10 = CARRY(GB1L11 & !MC1L8);


--MC1L11 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~604 at LCCOMB_X17_Y5_N18
MC1L11 = GB1L13 & !MC1L10 # !GB1L13 & (MC1L10 # GND);

--MC1L12 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~605 at LCCOMB_X17_Y5_N18
MC1L12 = CARRY(!MC1L10 # !GB1L13);


--MC1L13 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~606 at LCCOMB_X17_Y5_N20
MC1L13 = GB1L15 & (MC1L12 $ GND) # !GB1L15 & !MC1L12 & VCC;

--MC1L14 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~607 at LCCOMB_X17_Y5_N20
MC1L14 = CARRY(GB1L15 & !MC1L12);


--MC1L15 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~608 at LCCOMB_X17_Y5_N22
MC1L15 = GB1L17 & !MC1L14 # !GB1L17 & (MC1L14 # GND);

--MC1L16 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~609 at LCCOMB_X17_Y5_N22
MC1L16 = CARRY(!MC1L14 # !GB1L17);


--MC1L17 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~610 at LCCOMB_X17_Y5_N24
MC1L17 = GB1L19 & (MC1L16 $ GND) # !GB1L19 & !MC1L16 & VCC;

--MC1L18 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~611 at LCCOMB_X17_Y5_N24
MC1L18 = CARRY(GB1L19 & !MC1L16);


--MC1L19 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~612 at LCCOMB_X17_Y5_N26
MC1L19 = GB1L21 & !MC1L18 # !GB1L21 & (MC1L18 # GND);

--MC1L20 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~613 at LCCOMB_X17_Y5_N26
MC1L20 = CARRY(!MC1L18 # !GB1L21);


--MC1L21 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~614 at LCCOMB_X17_Y5_N28
MC1L21 = GB1L23 & (MC1L20 $ GND) # !GB1L23 & !MC1L20 & VCC;

--MC1L22 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~615 at LCCOMB_X17_Y5_N28
MC1L22 = CARRY(GB1L23 & !MC1L20);


--MC1L23 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~616 at LCCOMB_X17_Y5_N30
MC1L23 = GB1L25 & !MC1L22 # !GB1L25 & (MC1L22 # GND);

--MC1L24 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~617 at LCCOMB_X17_Y5_N30
MC1L24 = CARRY(!MC1L22 # !GB1L25);


--MC1L25 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~618 at LCCOMB_X17_Y4_N0
MC1L25 = GB1L27 & (MC1L24 $ GND) # !GB1L27 & !MC1L24 & VCC;

--MC1L26 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~619 at LCCOMB_X17_Y4_N0
MC1L26 = CARRY(GB1L27 & !MC1L24);


--MC1L27 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~620 at LCCOMB_X17_Y4_N2
MC1L27 = GB1L29 & !MC1L26 # !GB1L29 & (MC1L26 # GND);

--MC1L28 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~621 at LCCOMB_X17_Y4_N2
MC1L28 = CARRY(!MC1L26 # !GB1L29);


--MC1L29 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~622 at LCCOMB_X17_Y4_N4
MC1L29 = GB1L31 & (MC1L28 $ GND) # !GB1L31 & !MC1L28 & VCC;

--MC1L30 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~623 at LCCOMB_X17_Y4_N4
MC1L30 = CARRY(GB1L31 & !MC1L28);


--MC1L31 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~624 at LCCOMB_X17_Y4_N6
MC1L31 = GB1L33 & !MC1L30 # !GB1L33 & (MC1L30 # GND);

--MC1L32 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~625 at LCCOMB_X17_Y4_N6
MC1L32 = CARRY(!MC1L30 # !GB1L33);


--MC1L33 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~626 at LCCOMB_X17_Y4_N8
MC1L33 = GB1L35 & (MC1L32 $ GND) # !GB1L35 & !MC1L32 & VCC;

--MC1L34 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~627 at LCCOMB_X17_Y4_N8
MC1L34 = CARRY(GB1L35 & !MC1L32);


--MC1L35 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~628 at LCCOMB_X17_Y4_N10
MC1L35 = GB1L37 & !MC1L34 # !GB1L37 & (MC1L34 # GND);

--MC1L36 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~629 at LCCOMB_X17_Y4_N10
MC1L36 = CARRY(!MC1L34 # !GB1L37);


--MC1L37 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~630 at LCCOMB_X17_Y4_N12
MC1L37 = GB1L39 & (MC1L36 $ GND) # !GB1L39 & !MC1L36 & VCC;

--MC1L38 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~631 at LCCOMB_X17_Y4_N12
MC1L38 = CARRY(GB1L39 & !MC1L36);


--MC1L39 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~632 at LCCOMB_X17_Y4_N14
MC1L39 = GB1L41 & !MC1L38 # !GB1L41 & (MC1L38 # GND);

--MC1L40 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~633 at LCCOMB_X17_Y4_N14
MC1L40 = CARRY(!MC1L38 # !GB1L41);


--MC1L41 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~634 at LCCOMB_X17_Y4_N16
MC1L41 = GB1L43 & (MC1L40 $ GND) # !GB1L43 & !MC1L40 & VCC;

--MC1L42 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~635 at LCCOMB_X17_Y4_N16
MC1L42 = CARRY(GB1L43 & !MC1L40);


--MC1L43 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~636 at LCCOMB_X17_Y4_N18
MC1L43 = GB1L45 & !MC1L42 # !GB1L45 & (MC1L42 # GND);

--MC1L44 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~637 at LCCOMB_X17_Y4_N18
MC1L44 = CARRY(!MC1L42 # !GB1L45);


--MC1L45 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~638 at LCCOMB_X17_Y4_N20
MC1L45 = GB1L47 & (MC1L44 $ GND) # !GB1L47 & !MC1L44 & VCC;

--MC1L46 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~639 at LCCOMB_X17_Y4_N20
MC1L46 = CARRY(GB1L47 & !MC1L44);


--MC1L47 is lpm_divide0:inst8|lpm_divide:lpm_divide_component|lpm_divide_lej:auto_generated|sign_div_unsign_mkg:divider|alt_u_div_33e:divider|add_sub_4o8:add_sub_23|add_sub_cella[1]~640 at LCCOMB_X17_Y4_N22