hanshu.fit.eqn

用FPGA做的DDS函数信号发生器

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--DB1_q_a[0] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[0] at M4K_X11_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 10
--Port A Logical Depth: 256, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0] = DB1_q_a[0]_PORT_A_data_out_reg[0];

--DB1_q_a[8] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[8] = DB1_q_a[0]_PORT_A_data_out_reg[8];

--DB1_q_a[7] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[7] = DB1_q_a[0]_PORT_A_data_out_reg[7];

--DB1_q_a[6] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[6] = DB1_q_a[0]_PORT_A_data_out_reg[6];

--DB1_q_a[5] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[5] = DB1_q_a[0]_PORT_A_data_out_reg[5];

--DB1_q_a[4] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[4] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[4] = DB1_q_a[0]_PORT_A_data_out_reg[4];

--DB1_q_a[3] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[3] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[3] = DB1_q_a[0]_PORT_A_data_out_reg[3];

--DB1_q_a[2] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[2] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[2] = DB1_q_a[0]_PORT_A_data_out_reg[2];

--DB1_q_a[1] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[1] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[1] = DB1_q_a[0]_PORT_A_data_out_reg[1];

--DB1_q_a[9] is sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9] at M4K_X11_Y13
DB1_q_a[0]_PORT_A_address = BUS(BB1_output_dffea[16], BB1_output_dffea[17], BB1_output_dffea[18], BB1_output_dffea[19], BB1_output_dffea[20], BB1_output_dffea[21], BB1_output_dffea[22], BB1_output_dffea[23]);
DB1_q_a[0]_PORT_A_address_reg = DFFE(DB1_q_a[0]_PORT_A_address, DB1_q_a[0]_clock_0, , , );
DB1_q_a[0]_clock_0 = GLOBAL(A1L3);
DB1_q_a[0]_PORT_A_data_out = MEMORY(, , DB1_q_a[0]_PORT_A_address_reg, , , , , , DB1_q_a[0]_clock_0, , , , , );
DB1_q_a[0]_PORT_A_data_out_reg = DFFE(DB1_q_a[0]_PORT_A_data_out, DB1_q_a[0]_clock_0, , , );
DB1_q_a[9] = DB1_q_a[0]_PORT_A_data_out_reg[9];


--FB1_mac_out4 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4 at DSPOUT_X16_Y6_N2
--DSP Block Operation Mode: Simple Multiplier (18-bit)
FB1_mac_out4 = FB1_mac_mult3;

--FB1L105 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT1 at DSPOUT_X16_Y6_N2
FB1L105 = FB1L50;

--FB1L106 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT2 at DSPOUT_X16_Y6_N2
FB1L106 = FB1L51;

--FB1L107 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT3 at DSPOUT_X16_Y6_N2
FB1L107 = FB1L52;

--FB1L108 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT4 at DSPOUT_X16_Y6_N2
FB1L108 = FB1L53;

--FB1L109 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT5 at DSPOUT_X16_Y6_N2
FB1L109 = FB1L54;

--FB1L110 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT6 at DSPOUT_X16_Y6_N2
FB1L110 = FB1L55;

--FB1L111 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT7 at DSPOUT_X16_Y6_N2
FB1L111 = FB1L56;

--FB1L112 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT8 at DSPOUT_X16_Y6_N2
FB1L112 = FB1L57;

--FB1L113 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT9 at DSPOUT_X16_Y6_N2
FB1L113 = FB1L58;

--FB1L114 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT10 at DSPOUT_X16_Y6_N2
FB1L114 = FB1L59;

--FB1L115 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT11 at DSPOUT_X16_Y6_N2
FB1L115 = FB1L60;

--FB1L116 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT12 at DSPOUT_X16_Y6_N2
FB1L116 = FB1L61;

--FB1L117 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT13 at DSPOUT_X16_Y6_N2
FB1L117 = FB1L62;

--FB1L118 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT14 at DSPOUT_X16_Y6_N2
FB1L118 = FB1L63;

--FB1L119 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT15 at DSPOUT_X16_Y6_N2
FB1L119 = FB1L64;

--FB1L120 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT16 at DSPOUT_X16_Y6_N2
FB1L120 = FB1L65;

--FB1L121 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT17 at DSPOUT_X16_Y6_N2
FB1L121 = FB1L66;

--FB1L122 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT18 at DSPOUT_X16_Y6_N2
FB1L122 = FB1L67;

--FB1L123 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT19 at DSPOUT_X16_Y6_N2
FB1L123 = FB1L68;

--FB1L124 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT20 at DSPOUT_X16_Y6_N2
FB1L124 = FB1L69;

--FB1L125 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT21 at DSPOUT_X16_Y6_N2
FB1L125 = FB1L70;

--FB1L126 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT22 at DSPOUT_X16_Y6_N2
FB1L126 = FB1L71;

--FB1L127 is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|mac_out4~DATAOUT23 at DSPOUT_X16_Y6_N2
FB1L127 = FB1L72;


--FB1_w26w[0] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[0] at DSPOUT_X16_Y7_N2
--DSP Block Operation Mode: Simple Multiplier (18-bit)
FB1_w26w[0] = FB1_mac_mult1;

--FB1_w26w[1] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[1] at DSPOUT_X16_Y7_N2
FB1_w26w[1] = FB1L2;

--FB1_w26w[2] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[2] at DSPOUT_X16_Y7_N2
FB1_w26w[2] = FB1L3;

--FB1_w26w[3] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[3] at DSPOUT_X16_Y7_N2
FB1_w26w[3] = FB1L4;

--FB1_w26w[4] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[4] at DSPOUT_X16_Y7_N2
FB1_w26w[4] = FB1L5;

--FB1_w26w[5] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[5] at DSPOUT_X16_Y7_N2
FB1_w26w[5] = FB1L6;

--FB1_w26w[6] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[6] at DSPOUT_X16_Y7_N2
FB1_w26w[6] = FB1L7;

--FB1_w26w[7] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[7] at DSPOUT_X16_Y7_N2
FB1_w26w[7] = FB1L8;

--FB1_w26w[8] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[8] at DSPOUT_X16_Y7_N2
FB1_w26w[8] = FB1L9;

--FB1_w26w[9] is lpm_mult0:inst6|lpm_mult:lpm_mult_component|mult_o0r:auto_generated|w26w[9] at DSPOUT_X16_Y7_N2
FB1_w26w[9] = FB1L10;