nfenpin.txt

来自「N分频器则是一个简单的除N 计数器。分频器对脉冲加减电路的输出脉冲再进行N分频」· 文本 代码 · 共 128 行

 N分频器的VHDL语言描述
N分频器则是一个简单的除N 计数器。分频器对脉冲加减电路的输出脉冲再进行N分频，得到整个环路的输出信号Fout。同时，因为Fout = Clk/ 2 N = Fo ，因此通过改变分频值N 可以得到不同的环路中心频率Fo 。另外，模值N 的大小决定了DPLL 的鉴相灵敏度为π/ N 。以下描述以20分频为例。其VHDL语言描述如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clkdiv is
generic(n:integer:=20);
port(clk: in std_logic;
clkout_3:buffer std_logic);
end clkdiv;
architecture a of clkdiv is
signal cnt1,cnt2:integer:=0;
signal outtemp : std_logic;
signal lout: std_logic;
signal out3:std_logic:='0';
begin
process(clk)
begin
if clk'event and clk='1'then
if cnt1=n-1 then
cnt1<=0;
else
cnt1<=cnt1+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='0'then
if cnt2=n-1 then
cnt2<=0;
else 
cnt2<=cnt2+1;
end if;
end if;
end process;
process(cnt1,cnt2 )
begin
if ((n mod 2)=1) then
if cnt1=1 then
if cnt2=0 then
outtemp<='1';
else outtemp<='0';
end if;
elsif cnt1=(n+1)/2 then
if cnt2=(n+1)/2 then outtemp<='1';
else outtemp<='0';
end if;
else outtemp<='0';
end if;
else
if cnt1=1 then
outtemp<='1';
elsif (cnt1=(n/2+1)) then
outtemp<='1';
else
outtemp<='0';
end if; 
end if;
end process;
process(outtemp,clk)
begin
if ((n/=2) and (n/=1)) then
if outtemp'event and outtemp='1' then
clkout_3<=not clkout_3;
end if;
elsif (n=2) then
if(clk'event and clk='1')then
clkout_3<=not clkout_3;
end if;
else clkout_3<=clk;
end if;
end process;
end a;
数字锁相环的顶层VHDL语言描述
library ieee;
use ieee.std_logic_1164.all; 
library work;
entity suoxiang is 
	port
	(v1 :  in  std_logic;
		cp1 :  in  std_logic;
		en :  in  std_logic;
		d :  in  std_logic;
		c :  in  std_logic;
		b :  in  std_logic;
		a :  in  std_logic;
		cp2 :  in  std_logic;
		clr :  in  std_logic;
		v2 :  out  std_logic);
end suoxiang;
architecture bdf_type of suoxiang is 
component clkdiv
generic (n:integer);
	port(clk : in std_logic;
		 clkout_3 : out std_logic);
end component;
component count_k port (clk : in std_logic; j : in std_logic;  en : in std_logic;
		 d : in std_logic; c : in std_logic;  b : in std_logic;
		 a : in std_logic; r1 : out std_logic;  r2 : out std_logic);
end component;
component id port (idclk : in std_logic;
		 clr : in std_logic;
		 inc : in std_logic;
		 dec : in std_logic;
		 iout : out std_logic);
end component;
signal	synthesized_wire_0 :  std_logic;
signal	synthesized_wire_1 :  std_logic;
signal	synthesized_wire_2 :  std_logic;
signal	synthesized_wire_3 :  std_logic;
signal	synthesized_wire_4 :  std_logic;
begin 
v2 <= synthesized_wire_0;
b2v_inst : clkdiv generic map(n => 3)
port map(clk => synthesized_wire_0, clkout_3 => synthesized_wire_2);
b2v_inst2 : count_k
port map(clk => cp1, j => synthesized_wire_1,
		 en => en, d => d, c => c, b => b, a => a,
		 r1 => synthesized_wire_3, r2 => synthesized_wire_4);
synthesized_wire_1 <= v1 xor synthesized_wire_2;
b2v_inst4 : id
port map(idclk => cp2,clr => clr, inc => synthesized_wire_3,
		 dec => synthesized_wire_4,
		 iout => synthesized_wire_0);
end;