shuzisuoxiang.txt

数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比

数字锁相环顶层设计
下面给出详细描述DPLL的工作过程。
1．当环路失锁时，异或门鉴相器比较输入信号和输出信号之间的相位差异，并产生K变模可逆计数器的计数方向控制信号。
2．K变模可逆计数器根据计数方向控制信号调整计数值，控制信号为高进行减计数，并当计数值到达0时，输出借位脉冲信号；为低进行加计数，并当计数值达到预设的K模值时，输出进位脉冲信号。
3．脉冲加减电路则根据进位脉冲信号和借位脉冲信号在电路输出信号中进行脉冲的增加和扣除操作，来调整输出信号的频率。
4．重复上面的调整过程，当环路进入锁定状态时，异或门鉴相器的输出为一占空比50%的方波，而K变模可逆计数器则周期性地产生进位脉冲输出和借位脉冲输出，导致脉冲加减电路的输出周期性的加入和扣除半个脉冲[12]。
5.5.1数字锁相环的顶层VHDL语言描述
library ieee;
use ieee.std_logic_1164.all; 
library work;
entity suoxiang is 
	port
	(v1 :  in  std_logic;
		cp1 :  in  std_logic;
		en :  in  std_logic;
		d :  in  std_logic;
		c :  in  std_logic;
		b :  in  std_logic;
		a :  in  std_logic;
		cp2 :  in  std_logic;
		clr :  in  std_logic;
		v2 :  out  std_logic);
end suoxiang;
architecture bdf_type of suoxiang is 
component clkdiv
generic (n:integer);
	port(clk : in std_logic;
		 clkout_3 : out std_logic);
end component;
component count_k port (clk : in std_logic; j : in std_logic;  en : in std_logic;
		 d : in std_logic; c : in std_logic;  b : in std_logic;
		 a : in std_logic; r1 : out std_logic;  r2 : out std_logic);
end component;
component id port (idclk : in std_logic;
		 clr : in std_logic;
		 inc : in std_logic;
		 dec : in std_logic;
		 iout : out std_logic);
end component;
signal	synthesized_wire_0 :  std_logic;
signal	synthesized_wire_1 :  std_logic;
signal	synthesized_wire_2 :  std_logic;
signal	synthesized_wire_3 :  std_logic;
signal	synthesized_wire_4 :  std_logic;
begin 
v2 <= synthesized_wire_0;
b2v_inst : clkdiv generic map(n => 3)
port map(clk => synthesized_wire_0, clkout_3 => synthesized_wire_2);
b2v_inst2 : count_k
port map(clk => cp1, j => synthesized_wire_1,
		 en => en, d => d, c => c, b => b, a => a,
		 r1 => synthesized_wire_3, r2 => synthesized_wire_4);
synthesized_wire_1 <= v1 xor synthesized_wire_2;
b2v_inst4 : id
port map(idclk => cp2,clr => clr, inc => synthesized_wire_3,
		 dec => synthesized_wire_4,
		 iout => synthesized_wire_0);
end;