testctl.map.rpt

用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）

; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                         ;
+----------------------------------+-----------------+------------------------+----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path     ;
+----------------------------------+-----------------+------------------------+----------------------------------+
; second.v                         ; yes             ; User Verilog HDL File  ; D:/altera/file/fequency/second.v ;
+----------------------------------+-----------------+------------------------+----------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Estimated Total logic elements              ; 1         ;
;                                             ;           ;
; Total combinational functions               ; 1         ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 0         ;
;     -- 3 input functions                    ; 0         ;
;     -- <=2 input functions                  ; 1         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 1         ;
;     -- arithmetic mode                      ; 0         ;
;                                             ;           ;
; Total registers                             ; 0         ;
;     -- Dedicated logic registers            ; 0         ;
;     -- I/O registers                        ; 0         ;
;                                             ;           ;
; I/O pins                                    ; 1         ;
; Maximum fan-out node                        ; sec_out~1 ;
; Maximum fan-out                             ; 2         ;
; Total fan-out                               ; 2         ;
; Average fan-out                             ; 1.00      ;
+---------------------------------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |second                    ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 1    ; 0            ; |second             ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops               ;
+--------------------------------------------------------+---+
; Logic Cell Name                                        ;   ;
+--------------------------------------------------------+---+
; sec_out~0                                              ;   ;
; Number of logic cells representing combinational loops ; 1 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Aug 20 13:00:56 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fequency -c testctl
Info: Found 1 design units, including 1 entities, in source file testctl.v
    Info: Found entity 1: testctl
Info: Found 1 design units, including 1 entities, in source file cout4.v
    Info: Found entity 1: cout4
Info: Found 1 design units, including 1 entities, in source file reg32b.v
    Info: Found entity 1: reg32b
Info: Found 1 design units, including 1 entities, in source file fequency.bdf
    Info: Found entity 1: fequency
Info: Found 1 design units, including 1 entities, in source file second.v
    Info: Found entity 1: second
Info: Elaborating entity "second" for the top level hierarchy
Warning (10755): Verilog HDL warning at second.v(6): assignments to sec_out create a combinational loop
Info: Implemented 2 device resources after synthesis - the final resource count might be different
    Info: Implemented 0 input pins
    Info: Implemented 1 output pins
    Info: Implemented 1 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 158 megabytes
    Info: Processing ended: Wed Aug 20 13:01:05 2008
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:01