testctl.fit.rpt

用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）

; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                 ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Top  ; 0                 ; 2       ; Placement and Routing        ; Post-Synthesis Netlist ;           ;
+------+-------------------+---------+------------------------------+------------------------+-----------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/altera/file/fequency/testctl.pin.


+-------------------------------------------------------------------+
; Fitter Resource Usage Summary                                     ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Total logic elements                        ; 0 / 18,752 ( 0 % )  ;
;     -- Combinational with no register       ; 0                   ;
;     -- Register only                        ; 0                   ;
;     -- Combinational with a register        ; 0                   ;
;                                             ;                     ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 0                   ;
;     -- 3 input functions                    ; 0                   ;
;     -- <=2 input functions                  ; 0                   ;
;     -- Register only                        ; 0                   ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 0                   ;
;     -- arithmetic mode                      ; 0                   ;
;                                             ;                     ;
; Total registers*                            ; 0 / 19,130 ( 0 % )  ;
;     -- Dedicated logic registers            ; 0 / 18,752 ( 0 % )  ;
;     -- I/O registers                        ; 0 / 378 ( 0 % )     ;
;                                             ;                     ;
; Total LABs:  partially or completely used   ; 1 / 1,172 ( < 1 % ) ;
; User inserted logic elements                ; 0                   ;
; Virtual pins                                ; 0                   ;
; I/O pins                                    ; 1 / 142 ( < 1 % )   ;
;     -- Clock pins                           ; 0 / 8 ( 0 % )       ;
; Global signals                              ; 0                   ;
; M4Ks                                        ; 0 / 52 ( 0 % )      ;
; Total memory bits                           ; 0 / 239,616 ( 0 % ) ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 52 ( 0 % )      ;
; PLLs                                        ; 0 / 4 ( 0 % )       ;
; Global clocks                               ; 0 / 16 ( 0 % )      ;
; JTAGs                                       ; 0 / 1 ( 0 % )       ;
; Maximum fan-out node                        ; sec_out~1           ;
; Maximum fan-out                             ; 2                   ;
; Highest non-global fan-out signal           ; sec_out~1           ;
; Highest non-global fan-out                  ; 2                   ;
; Total fan-out                               ; 2                   ;
; Average fan-out                             ; 0.40                ;
+---------------------------------------------+---------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                              ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; sec_out ; 56    ; 1        ; 0            ; 2            ; 0           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; Fitter               ; 0 pF ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+


+-----------------------------------------------------------+
; I/O Bank Usage                                            ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ;
+----------+-----------------+---------------+--------------+
; 1        ; 1 / 19 ( 5 % )  ; 3.3V          ; --           ;
; 2        ; 2 / 16 ( 13 % ) ; 3.3V          ; --           ;
; 3        ; 0 / 18 ( 0 % )  ; 3.3V          ; --           ;
; 4        ; 0 / 17 ( 0 % )  ; 3.3V          ; --           ;
; 5        ; 0 / 20 ( 0 % )  ; 3.3V          ; --           ;
; 6        ; 1 / 18 ( 6 % )  ; 3.3V          ; --           ;
; 7        ; 0 / 16 ( 0 % )  ; 3.3V          ; --           ;
; 8        ; 0 / 18 ( 0 % )  ; 3.3V          ; --           ;
+----------+-----------------+---------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                       ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                           ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;