testctl.fit.rpt

用VHDL语言描述的工程实例频率计（在quartus 7.2中使用）

Fitter report for testctl
Wed Aug 20 13:01:23 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Partition Preservation Settings
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Non-Global High Fan-Out Signals
 14. Interconnect Usage Summary
 15. LAB Logic Elements
 16. LAB Signals Sourced
 17. LAB Signals Sourced Out
 18. Fitter Device Options
 19. Operating Settings and Conditions
 20. Advanced Data - General
 21. Advanced Data - Placement Preparation
 22. Advanced Data - Placement
 23. Advanced Data - Routing
 24. Fitter Messages
 25. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Fitter Summary                                                                ;
+------------------------------------+------------------------------------------+
; Fitter Status                      ; Successful - Wed Aug 20 13:01:23 2008    ;
; Quartus II Version                 ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name                      ; testctl                                  ;
; Top-level Entity Name              ; second                                   ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C20Q240C8                             ;
; Timing Models                      ; Final                                    ;
; Total logic elements               ; 0 / 18,752 ( 0 % )                       ;
;     Total combinational functions  ; 0 / 18,752 ( 0 % )                       ;
;     Dedicated logic registers      ; 0 / 18,752 ( 0 % )                       ;
; Total registers                    ; 0                                        ;
; Total pins                         ; 1 / 142 ( < 1 % )                        ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0 / 239,616 ( 0 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % )                           ;
; Total PLLs                         ; 0 / 4 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP2C20Q240C8                   ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;