light.map.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真交通灯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 22:08:43 2007 " "Info: Processing started: Sat Dec 08 22:08:43 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off light -c light " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off light -c light" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "light.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file light.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 light-one " "Info: Found design unit 1: light-one" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 light " "Info: Found entity 1: light" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "light " "Info: Elaborating entity \"light\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "light.vhd(37) " "Info: VHDL Case Statement information at light.vhd(37): OTHERS choice is never selected" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 37 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp light.vhd(39) " "Warning: VHDL Process Statement warning at light.vhd(39): signal \"temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 39 0 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|light\|current_state 3 0 " "Info: State machine \"\|light\|current_state\" contains 3 states and 0 state bits" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 16 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|light\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|light\|current_state\"" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 16 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|light\|current_state " "Info: Encoding result for state machine \"\|light\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.yellow " "Info: Encoded state bit \"current_state.yellow\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.green " "Info: Encoded state bit \"current_state.green\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.red " "Info: Encoded state bit \"current_state.red\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|light\|current_state.red 000 " "Info: State \"\|light\|current_state.red\" uses code string \"000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|light\|current_state.green 011 " "Info: State \"\|light\|current_state.green\" uses code string \"011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|light\|current_state.yellow 101 " "Info: State \"\|light\|current_state.yellow\" uses code string \"101\"" {  } {  } 0}  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 16 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "15 " "Info: Implemented 15 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "10 " "Info: Implemented 10 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 22:08:44 2007 " "Info: Processing ended: Sat Dec 08 22:08:44 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}