light.tan.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真交通灯

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register time\[2\] register time\[3\] 337.27 MHz 2.965 ns Internal " "Info: Clock \"clk\" has Internal fmax of 337.27 MHz between source register \"time\[2\]\" and destination register \"time\[3\]\" (period= 2.965 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.763 ns + Longest register register " "Info: + Longest register to register delay is 2.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time\[2\] 1 REG LC_X2_Y1_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N7; Fanout = 4; REG Node = 'time\[2\]'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "" { time[2] } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.454 ns) 0.882 ns reduce_nor~114 2 COMB LC_X2_Y1_N4 1 " "Info: 2: + IC(0.428 ns) + CELL(0.454 ns) = 0.882 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; COMB Node = 'reduce_nor~114'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "0.882 ns" { time[2] reduce_nor~114 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.340 ns) 1.540 ns reduce_nor~0 3 COMB LC_X2_Y1_N1 8 " "Info: 3: + IC(0.318 ns) + CELL(0.340 ns) = 1.540 ns; Loc. = LC_X2_Y1_N1; Fanout = 8; COMB Node = 'reduce_nor~0'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "0.658 ns" { reduce_nor~114 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.856 ns) 2.763 ns time\[3\] 4 REG LC_X2_Y1_N8 4 " "Info: 4: + IC(0.367 ns) + CELL(0.856 ns) = 2.763 ns; Loc. = LC_X2_Y1_N8; Fanout = 4; REG Node = 'time\[3\]'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "1.223 ns" { reduce_nor~0 time[3] } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns 59.72 % " "Info: Total cell delay = 1.650 ns ( 59.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.113 ns 40.28 % " "Info: Total interconnect delay = 1.113 ns ( 40.28 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.763 ns" { time[2] reduce_nor~114 reduce_nor~0 time[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.763 ns" { time[2] reduce_nor~114 reduce_nor~0 time[3] } { 0.000ns 0.428ns 0.318ns 0.367ns } { 0.000ns 0.454ns 0.340ns 0.856ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.099 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "" { clk } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns time\[3\] 2 REG LC_X2_Y1_N8 4 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y1_N8; Fanout = 4; REG Node = 'time\[3\]'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "0.969 ns" { clk time[3] } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.099 ns" { clk time[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 time[3] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.099 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "" { clk } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns time\[2\] 2 REG LC_X2_Y1_N7 4 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y1_N7; Fanout = 4; REG Node = 'time\[2\]'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "0.969 ns" { clk time[2] } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.099 ns" { clk time[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 time[2] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.099 ns" { clk time[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 time[3] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.099 ns" { clk time[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 time[2] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 17 -1 0 } }  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.763 ns" { time[2] reduce_nor~114 reduce_nor~0 time[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.763 ns" { time[2] reduce_nor~114 reduce_nor~0 time[3] } { 0.000ns 0.428ns 0.318ns 0.367ns } { 0.000ns 0.454ns 0.340ns 0.856ns } } } { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.099 ns" { clk time[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 time[3] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.099 ns" { clk time[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 time[2] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk cout\[0\] current_state.yellow 4.983 ns register " "Info: tco from clock \"clk\" to destination pin \"cout\[0\]\" through register \"current_state.yellow\" is 4.983 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.099 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "" { clk } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns current_state.yellow 2 REG LC_X2_Y1_N3 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y1_N3; Fanout = 2; REG Node = 'current_state.yellow'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "0.969 ns" { clk current_state.yellow } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.099 ns" { clk current_state.yellow } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 current_state.yellow } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.711 ns + Longest register pin " "Info: + Longest register to pin delay is 2.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.yellow 1 REG LC_X2_Y1_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N3; Fanout = 2; REG Node = 'current_state.yellow'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "" { current_state.yellow } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(1.634 ns) 2.711 ns cout\[0\] 2 PIN PIN_36 0 " "Info: 2: + IC(1.077 ns) + CELL(1.634 ns) = 2.711 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'cout\[0\]'" {  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.711 ns" { current_state.yellow cout[0] } "NODE_NAME" } "" } } { "light.vhd" "" { Text "D:/eda设计/VHDL/红绿灯/light.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns 60.27 % " "Info: Total cell delay = 1.634 ns ( 60.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.077 ns 39.73 % " "Info: Total interconnect delay = 1.077 ns ( 39.73 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.711 ns" { current_state.yellow cout[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.711 ns" { current_state.yellow cout[0] } { 0.000ns 1.077ns } { 0.000ns 1.634ns } } }  } 0}  } { { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.099 ns" { clk current_state.yellow } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { clk clk~out0 current_state.yellow } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" "" { Report "D:/eda设计/VHDL/红绿灯/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/eda设计/VHDL/红绿灯/db/light.quartus_db" { Floorplan "D:/eda设计/VHDL/红绿灯/" "" "2.711 ns" { current_state.yellow cout[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.711 ns" { current_state.yellow cout[0] } { 0.000ns 1.077ns } { 0.000ns 1.634ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 22:08:52 2007 " "Info: Processing ended: Sat Dec 08 22:08:52 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}