speaker.tan.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真歌曲刘德华的《月老》

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "speaker:u3\|\\divideclk:count4\[2\] " "Info: Detected ripple clock \"speaker:u3\|\\divideclk:count4\[2\]\" as buffer" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|\\divideclk:count4\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "speaker:u3\|\\divideclk:count4\[3\] " "Info: Detected ripple clock \"speaker:u3\|\\divideclk:count4\[3\]\" as buffer" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|\\divideclk:count4\[3\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "speaker:u3\|LessThan~40 " "Info: Detected gated clock \"speaker:u3\|LessThan~40\" as buffer" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|LessThan~40" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "speaker:u3\|fullspks " "Info: Detected ripple clock \"speaker:u3\|fullspks\" as buffer" {  } { { "speaker.vhd" "" { Text "D:/eda设计/VHDL/月老/speaker.vhd" 10 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|fullspks" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk12MHZ register speaker:u3\|\\genspks:count11\[10\] register speaker:u3\|\\genspks:count11\[10\] 242.37 MHz 4.126 ns Internal " "Info: Clock \"clk12MHZ\" has Internal fmax of 242.37 MHz between source register \"speaker:u3\|\\genspks:count11\[10\]\" and destination register \"speaker:u3\|\\genspks:count11\[10\]\" (period= 4.126 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.767 ns + Longest register register " "Info: + Longest register to register delay is 3.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speaker:u3\|\\genspks:count11\[10\] 1 REG LC_X9_Y6_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N5; Fanout = 2; REG Node = 'speaker:u3\|\\genspks:count11\[10\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "" { speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.954 ns) + CELL(0.340 ns) 1.294 ns speaker:u3\|reduce_nor~70 2 COMB LC_X9_Y7_N4 2 " "Info: 2: + IC(0.954 ns) + CELL(0.340 ns) = 1.294 ns; Loc. = LC_X9_Y7_N4; Fanout = 2; COMB Node = 'speaker:u3\|reduce_nor~70'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "1.294 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.345 ns) + CELL(0.225 ns) 1.864 ns speaker:u3\|reduce_nor~71 3 COMB LC_X9_Y7_N2 11 " "Info: 3: + IC(0.345 ns) + CELL(0.225 ns) = 1.864 ns; Loc. = LC_X9_Y7_N2; Fanout = 11; COMB Node = 'speaker:u3\|reduce_nor~71'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "0.570 ns" { speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.960 ns) + CELL(0.943 ns) 3.767 ns speaker:u3\|\\genspks:count11\[10\] 4 REG LC_X9_Y6_N5 2 " "Info: 4: + IC(0.960 ns) + CELL(0.943 ns) = 3.767 ns; Loc. = LC_X9_Y6_N5; Fanout = 2; REG Node = 'speaker:u3\|\\genspks:count11\[10\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "1.903 ns" { speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.508 ns 40.03 % " "Info: Total cell delay = 1.508 ns ( 40.03 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.259 ns 59.97 % " "Info: Total interconnect delay = 2.259 ns ( 59.97 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.767 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.767 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } { 0.000ns 0.954ns 0.345ns 0.960ns } { 0.000ns 0.340ns 0.225ns 0.943ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.157 ns - Smallest " "Info: - Smallest clock skew is -0.157 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk12MHZ destination 6.325 ns + Shortest register " "Info: + Shortest clock path from clock \"clk12MHZ\" to destination register is 6.325 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk12MHZ 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'clk12MHZ'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "" { clk12MHZ } "NODE_NAME" } "" } } { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.720 ns) 2.272 ns speaker:u3\|\\divideclk:count4\[2\] 2 REG LC_X7_Y5_N5 3 " "Info: 2: + IC(0.422 ns) + CELL(0.720 ns) = 2.272 ns; Loc. = LC_X7_Y5_N5; Fanout = 3; REG Node = 'speaker:u3\|\\divideclk:count4\[2\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "1.142 ns" { clk12MHZ speaker:u3|\divideclk:count4[2] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.088 ns) 2.766 ns speaker:u3\|LessThan~40 3 COMB LC_X7_Y5_N6 16 " "Info: 3: + IC(0.406 ns) + CELL(0.088 ns) = 2.766 ns; Loc. = LC_X7_Y5_N6; Fanout = 16; COMB Node = 'speaker:u3\|LessThan~40'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "0.494 ns" { speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.012 ns) + CELL(0.547 ns) 6.325 ns speaker:u3\|\\genspks:count11\[10\] 4 REG LC_X9_Y6_N5 2 " "Info: 4: + IC(3.012 ns) + CELL(0.547 ns) = 6.325 ns; Loc. = LC_X9_Y6_N5; Fanout = 2; REG Node = 'speaker:u3\|\\genspks:count11\[10\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.559 ns" { speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.485 ns 39.29 % " "Info: Total cell delay = 2.485 ns ( 39.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.840 ns 60.71 % " "Info: Total interconnect delay = 3.840 ns ( 60.71 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "6.325 ns" { clk12MHZ speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.325 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.422ns 0.406ns 3.012ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk12MHZ source 6.482 ns - Longest register " "Info: - Longest clock path from clock \"clk12MHZ\" to source register is 6.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk12MHZ 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'clk12MHZ'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "" { clk12MHZ } "NODE_NAME" } "" } } { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.720 ns) 2.272 ns speaker:u3\|\\divideclk:count4\[3\] 2 REG LC_X7_Y5_N9 2 " "Info: 2: + IC(0.422 ns) + CELL(0.720 ns) = 2.272 ns; Loc. = LC_X7_Y5_N9; Fanout = 2; REG Node = 'speaker:u3\|\\divideclk:count4\[3\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "1.142 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.225 ns) 2.923 ns speaker:u3\|LessThan~40 3 COMB LC_X7_Y5_N6 16 " "Info: 3: + IC(0.426 ns) + CELL(0.225 ns) = 2.923 ns; Loc. = LC_X7_Y5_N6; Fanout = 16; COMB Node = 'speaker:u3\|LessThan~40'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "0.651 ns" { speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.012 ns) + CELL(0.547 ns) 6.482 ns speaker:u3\|\\genspks:count11\[10\] 4 REG LC_X9_Y6_N5 2 " "Info: 4: + IC(3.012 ns) + CELL(0.547 ns) = 6.482 ns; Loc. = LC_X9_Y6_N5; Fanout = 2; REG Node = 'speaker:u3\|\\genspks:count11\[10\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.559 ns" { speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns 40.45 % " "Info: Total cell delay = 2.622 ns ( 40.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.860 ns 59.55 % " "Info: Total interconnect delay = 3.860 ns ( 59.55 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "6.482 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.482 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.422ns 0.426ns 3.012ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "6.325 ns" { clk12MHZ speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.325 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.422ns 0.406ns 3.012ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } } { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "6.482 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.482 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.422ns 0.426ns 3.012ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.767 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.767 ns" { speaker:u3|\genspks:count11[10] speaker:u3|reduce_nor~70 speaker:u3|reduce_nor~71 speaker:u3|\genspks:count11[10] } { 0.000ns 0.954ns 0.345ns 0.960ns } { 0.000ns 0.340ns 0.225ns 0.943ns } } } { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "6.325 ns" { clk12MHZ speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.325 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[2] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.422ns 0.406ns 3.012ns } { 0.000ns 1.130ns 0.720ns 0.088ns 0.547ns } } } { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "6.482 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.482 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|\genspks:count11[10] } { 0.000ns 0.000ns 0.422ns 0.426ns 3.012ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk8HZ memory notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|ram_block1a0~porta_address_reg0 memory notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[1\] 256.02 MHz 3.906 ns Internal " "Info: Clock \"clk8HZ\" has Internal fmax of 256.02 MHz between source memory \"notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[1\]\" (period= 3.906 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.323 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X13_Y8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y8; Fanout = 4; MEM Node = 'notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.323 ns) 3.323 ns notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[1\] 2 MEM M4K_X13_Y8 13 " "Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X13_Y8; Fanout = 13; MEM Node = 'notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[1\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.323 ns" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.323 ns 100.00 % " "Info: Total cell delay = 3.323 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.323 ns" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.323 ns" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } { 0.000ns 0.000ns } { 0.000ns 3.323ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8HZ destination 2.136 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk8HZ\" to destination memory is 2.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk8HZ 1 CLK PIN_17 20 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 20; CLK Node = 'clk8HZ'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "" { clk8HZ } "NODE_NAME" } "" } } { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.545 ns) 2.136 ns notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[1\] 2 MEM M4K_X13_Y8 13 " "Info: 2: + IC(0.461 ns) + CELL(0.545 ns) = 2.136 ns; Loc. = M4K_X13_Y8; Fanout = 13; MEM Node = 'notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[1\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "1.006 ns" { clk8HZ notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.675 ns 78.42 % " "Info: Total cell delay = 1.675 ns ( 78.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.58 % " "Info: Total interconnect delay = 0.461 ns ( 21.58 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "2.136 ns" { clk8HZ notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.136 ns" { clk8HZ clk8HZ~out0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.545ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8HZ source 2.147 ns - Longest memory " "Info: - Longest clock path from clock \"clk8HZ\" to source memory is 2.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk8HZ 1 CLK PIN_17 20 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 20; CLK Node = 'clk8HZ'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "" { clk8HZ } "NODE_NAME" } "" } } { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.556 ns) 2.147 ns notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X13_Y8 4 " "Info: 2: + IC(0.461 ns) + CELL(0.556 ns) = 2.147 ns; Loc. = M4K_X13_Y8; Fanout = 4; MEM Node = 'notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "1.017 ns" { clk8HZ notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns 78.53 % " "Info: Total cell delay = 1.686 ns ( 78.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.47 % " "Info: Total interconnect delay = 0.461 ns ( 21.47 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "2.147 ns" { clk8HZ notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.147 ns" { clk8HZ clk8HZ~out0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.556ns } } }  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "2.136 ns" { clk8HZ notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.136 ns" { clk8HZ clk8HZ~out0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.545ns } } } { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "2.147 ns" { clk8HZ notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.147 ns" { clk8HZ clk8HZ~out0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.556ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.323 ns" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.323 ns" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } { 0.000ns 0.000ns } { 0.000ns 3.323ns } } } { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "2.136 ns" { clk8HZ notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.136 ns" { clk8HZ clk8HZ~out0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|q_a[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.545ns } } } { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "2.147 ns" { clk8HZ notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.147 ns" { clk8HZ clk8HZ~out0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_kiq:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.556ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk12MHZ spkout speaker:u3\|\\delayspks:count2 11.193 ns register " "Info: tco from clock \"clk12MHZ\" to destination pin \"spkout\" through register \"speaker:u3\|\\delayspks:count2\" is 11.193 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk12MHZ source 7.647 ns + Longest register " "Info: + Longest clock path from clock \"clk12MHZ\" to source register is 7.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk12MHZ 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'clk12MHZ'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "" { clk12MHZ } "NODE_NAME" } "" } } { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.720 ns) 2.272 ns speaker:u3\|\\divideclk:count4\[3\] 2 REG LC_X7_Y5_N9 2 " "Info: 2: + IC(0.422 ns) + CELL(0.720 ns) = 2.272 ns; Loc. = LC_X7_Y5_N9; Fanout = 2; REG Node = 'speaker:u3\|\\divideclk:count4\[3\]'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "1.142 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.225 ns) 2.923 ns speaker:u3\|LessThan~40 3 COMB LC_X7_Y5_N6 16 " "Info: 3: + IC(0.426 ns) + CELL(0.225 ns) = 2.923 ns; Loc. = LC_X7_Y5_N6; Fanout = 16; COMB Node = 'speaker:u3\|LessThan~40'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "0.651 ns" { speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.012 ns) + CELL(0.720 ns) 6.655 ns speaker:u3\|fullspks 4 REG LC_X9_Y7_N2 1 " "Info: 4: + IC(3.012 ns) + CELL(0.720 ns) = 6.655 ns; Loc. = LC_X9_Y7_N2; Fanout = 1; REG Node = 'speaker:u3\|fullspks'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.732 ns" { speaker:u3|LessThan~40 speaker:u3|fullspks } "NODE_NAME" } "" } } { "speaker.vhd" "" { Text "D:/eda设计/VHDL/月老/speaker.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.547 ns) 7.647 ns speaker:u3\|\\delayspks:count2 5 REG LC_X9_Y7_N0 2 " "Info: 5: + IC(0.445 ns) + CELL(0.547 ns) = 7.647 ns; Loc. = LC_X9_Y7_N0; Fanout = 2; REG Node = 'speaker:u3\|\\delayspks:count2'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "0.992 ns" { speaker:u3|fullspks speaker:u3|\delayspks:count2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.342 ns 43.70 % " "Info: Total cell delay = 3.342 ns ( 43.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.305 ns 56.30 % " "Info: Total interconnect delay = 4.305 ns ( 56.30 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "7.647 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|fullspks speaker:u3|\delayspks:count2 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.647 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|fullspks speaker:u3|\delayspks:count2 } { 0.000ns 0.000ns 0.422ns 0.426ns 3.012ns 0.445ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.720ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.373 ns + Longest register pin " "Info: + Longest register to pin delay is 3.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speaker:u3\|\\delayspks:count2 1 REG LC_X9_Y7_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N0; Fanout = 2; REG Node = 'speaker:u3\|\\delayspks:count2'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "" { speaker:u3|\delayspks:count2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.751 ns) + CELL(1.622 ns) 3.373 ns spkout 2 PIN PIN_129 0 " "Info: 2: + IC(1.751 ns) + CELL(1.622 ns) = 3.373 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'spkout'" {  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.373 ns" { speaker:u3|\delayspks:count2 spkout } "NODE_NAME" } "" } } { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 48.09 % " "Info: Total cell delay = 1.622 ns ( 48.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.751 ns 51.91 % " "Info: Total interconnect delay = 1.751 ns ( 51.91 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.373 ns" { speaker:u3|\delayspks:count2 spkout } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.373 ns" { speaker:u3|\delayspks:count2 spkout } { 0.000ns 1.751ns } { 0.000ns 1.622ns } } }  } 0}  } { { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "7.647 ns" { clk12MHZ speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|fullspks speaker:u3|\delayspks:count2 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.647 ns" { clk12MHZ clk12MHZ~out0 speaker:u3|\divideclk:count4[3] speaker:u3|LessThan~40 speaker:u3|fullspks speaker:u3|\delayspks:count2 } { 0.000ns 0.000ns 0.422ns 0.426ns 3.012ns 0.445ns } { 0.000ns 1.130ns 0.720ns 0.225ns 0.720ns 0.547ns } } } { "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/月老/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/月老/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/月老/" "" "3.373 ns" { speaker:u3|\delayspks:count2 spkout } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.373 ns" { speaker:u3|\delayspks:count2 spkout } { 0.000ns 1.751ns } { 0.000ns 1.622ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 14 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 04 20:26:52 2007 " "Info: Processing ended: Tue Dec 04 20:26:52 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}