speaker.tan.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真歌曲刘德华的《月老》

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[5\] " "Info: Node \"tonetaba:u2\|tone\[5\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[4\] " "Info: Node \"tonetaba:u2\|tone\[4\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[3\] " "Info: Node \"tonetaba:u2\|tone\[3\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[2\] " "Info: Node \"tonetaba:u2\|tone\[2\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[8\] " "Info: Node \"tonetaba:u2\|tone\[8\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[1\] " "Info: Node \"tonetaba:u2\|tone\[1\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "tonetaba:u2\|tone\[0\] " "Info: Node \"tonetaba:u2\|tone\[0\]\"" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk12MHZ " "Info: Assuming node \"clk12MHZ\" is an undefined clock" {  } { { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 4 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk12MHZ" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk8HZ " "Info: Assuming node \"clk8HZ\" is an undefined clock" {  } { { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 5 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk8HZ" } } } }  } 0}  } {  } 0}