speaker.map.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真歌曲刘德华的《月老》

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 04 20:26:42 2007 " "Info: Processing started: Tue Dec 04 20:26:42 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off speaker -c speaker " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off speaker -c speaker" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "speaker.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file speaker.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 speaker-one " "Info: Found design unit 1: speaker-one" {  } { { "speaker.vhd" "" { Text "D:/eda设计/VHDL/月老/speaker.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 speaker " "Info: Found entity 1: speaker" {  } { { "speaker.vhd" "" { Text "D:/eda设计/VHDL/月老/speaker.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tonetaba.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tonetaba.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tonetaba-one " "Info: Found design unit 1: tonetaba-one" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 7 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 tonetaba " "Info: Found entity 1: tonetaba" {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "notetabs.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file notetabs.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 notetabs-one " "Info: Found design unit 1: notetabs-one" {  } { { "notetabs.vhd" "" { Text "D:/eda设计/VHDL/月老/notetabs.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 notetabs " "Info: Found entity 1: notetabs" {  } { { "notetabs.vhd" "" { Text "D:/eda设计/VHDL/月老/notetabs.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "songer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file songer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 songer-one " "Info: Found design unit 1: songer-one" {  } { { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 songer " "Info: Found entity 1: songer" {  } { { "songer.vhd" "" { Text "D:/eda设计/VHDL/月老/songer.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "songer " "Info: Elaborating entity \"songer\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "notetabs notetabs:u1 " "Info: Elaborating entity \"notetabs\" for hierarchy \"notetabs:u1\"" {  } { { "songer.vhd" "u1" { Text "D:/eda设计/VHDL/月老/songer.vhd" 25 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter notetabs.vhd(18) " "Warning: VHDL Process Statement warning at notetabs.vhd(18): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "notetabs.vhd" "" { Text "D:/eda设计/VHDL/月老/notetabs.vhd" 18 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "music.vhd 2 1 " "Info: Using design file music.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 music-SYN " "Info: Found design unit 1: music-SYN" {  } { { "music.vhd" "" { Text "D:/eda设计/VHDL/月老/music.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 music " "Info: Found entity 1: music" {  } { { "music.vhd" "" { Text "D:/eda设计/VHDL/月老/music.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "music notetabs:u1\|music:u1 " "Info: Elaborating entity \"music\" for hierarchy \"notetabs:u1\|music:u1\"" {  } { { "notetabs.vhd" "u1" { Text "D:/eda设计/VHDL/月老/notetabs.vhd" 22 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram notetabs:u1\|music:u1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"notetabs:u1\|music:u1\|altsyncram:altsyncram_component\"" {  } { { "music.vhd" "altsyncram_component" { Text "D:/eda设计/VHDL/月老/music.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_kiq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kiq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_kiq " "Info: Found entity 1: altsyncram_kiq" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_kiq notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated " "Info: Elaborating entity \"altsyncram_kiq\" for hierarchy \"notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tonetaba tonetaba:u2 " "Info: Elaborating entity \"tonetaba\" for hierarchy \"tonetaba:u2\"" {  } { { "songer.vhd" "u2" { Text "D:/eda设计/VHDL/月老/songer.vhd" 26 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "tone tonetaba.vhd(9) " "Warning: VHDL Process Statement warning at tonetaba.vhd(9): signal or variable \"tone\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"tone\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 9 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "speaker speaker:u3 " "Info: Elaborating entity \"speaker\" for hierarchy \"speaker:u3\"" {  } { { "songer.vhd" "u3" { Text "D:/eda设计/VHDL/月老/songer.vhd" 27 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "speaker:u3\|spks speaker:u3\|\\delayspks:count2 " "Info: Duplicate register \"speaker:u3\|spks\" merged to single register \"speaker:u3\|\\delayspks:count2\"" {  } { { "speaker.vhd" "" { Text "D:/eda设计/VHDL/月老/speaker.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[0\] " "Warning: Latch tonetaba:u2\|tone\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[1\] " "Warning: Latch tonetaba:u2\|tone\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[2\] " "Warning: Latch tonetaba:u2\|tone\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[3\] " "Warning: Latch tonetaba:u2\|tone\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[4\] " "Warning: Latch tonetaba:u2\|tone\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[3\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[5\] " "Warning: Latch tonetaba:u2\|tone\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[6\] " "Warning: Latch tonetaba:u2\|tone\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[7\] " "Warning: Latch tonetaba:u2\|tone\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[8\] " "Warning: Latch tonetaba:u2\|tone\[8\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[9\] " "Warning: Latch tonetaba:u2\|tone\[9\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[0\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "tonetaba:u2\|tone\[10\] " "Warning: Latch tonetaba:u2\|tone\[10\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_kiq:auto_generated\|q_a\[1\]" {  } { { "db/altsyncram_kiq.tdf" "" { Text "D:/eda设计/VHDL/月老/db/altsyncram_kiq.tdf" 38 2 0 } }  } 0}  } { { "tonetaba.vhd" "" { Text "D:/eda设计/VHDL/月老/tonetaba.vhd" 5 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "64 " "Info: Implemented 64 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "57 " "Info: Implemented 57 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 04 20:26:44 2007 " "Info: Processing ended: Tue Dec 04 20:26:44 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}