time_lock.fit.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.684 ns register register " "Info: Estimated most critical path is register to register delay of 0.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lock_time0\[0\] 1 REG LAB_X4_Y1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y1; Fanout = 2; REG Node = 'lock_time0\[0\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time0[0] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.568 ns) 0.684 ns lock_time0\[4\] 2 REG LAB_X4_Y1 2 " "Info: 2: + IC(0.116 ns) + CELL(0.568 ns) = 0.684 ns; Loc. = LAB_X4_Y1; Fanout = 2; REG Node = 'lock_time0\[4\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.684 ns" { lock_time0[0] lock_time0[4] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.568 ns 83.04 % " "Info: Total cell delay = 0.568 ns ( 83.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.116 ns 16.96 % " "Info: Total interconnect delay = 0.116 ns ( 16.96 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.684 ns" { lock_time0[0] lock_time0[4] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 21:54:22 2008 " "Info: Processing ended: Sun Mar 02 21:54:22 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}