time_lock.fit.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 21:54:13 2008 " "Info: Processing started: Sun Mar 02 21:54:13 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off time_lock -c time_lock " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off time_lock -c time_lock" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "time_lock EP1C3T144C6 " "Info: Selected device EP1C3T144C6 for design \"time_lock\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C6 " "Info: Device EP1C6T144C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "28 28 " "Info: No exact pin location assignment(s) for 28 pins of 28 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[0\] " "Info: Pin lock_time\[0\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[0\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[0] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[1\] " "Info: Pin lock_time\[1\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[1\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[1] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[2\] " "Info: Pin lock_time\[2\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[2\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[2] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[3\] " "Info: Pin lock_time\[3\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[3\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[3] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[4\] " "Info: Pin lock_time\[4\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[4\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[4] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[5\] " "Info: Pin lock_time\[5\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[5\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[5] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[6\] " "Info: Pin lock_time\[6\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[6\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[6] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[7\] " "Info: Pin lock_time\[7\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[7\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[7] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[8\] " "Info: Pin lock_time\[8\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[8\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[8] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[9\] " "Info: Pin lock_time\[9\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[9\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[9] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[10\] " "Info: Pin lock_time\[10\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[10\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[10] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[11\] " "Info: Pin lock_time\[11\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[11\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[11] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[12\] " "Info: Pin lock_time\[12\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[12\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[12] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[12] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[13\] " "Info: Pin lock_time\[13\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[13\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[13] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[14\] " "Info: Pin lock_time\[14\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[14\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[14] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[14] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock_time\[15\] " "Info: Pin lock_time\[15\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lock_time\[15\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time[15] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { lock_time[15] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keydown " "Info: Pin keydown not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keydown" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { keydown } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { keydown } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "reset " "Info: Pin reset not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { reset } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { reset } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[8\] " "Info: Pin key\[8\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[8\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[8] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[0\] " "Info: Pin key\[0\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[0\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[0] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[7\] " "Info: Pin key\[7\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[7\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[7] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[6\] " "Info: Pin key\[6\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[6\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[6] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[5\] " "Info: Pin key\[5\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[5\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[5] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[1\] " "Info: Pin key\[1\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[1\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[1] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[9\] " "Info: Pin key\[9\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[9\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[9] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[3\] " "Info: Pin key\[3\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[3\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[3] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[2\] " "Info: Pin key\[2\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[2\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[2] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "key\[4\] " "Info: Pin key\[4\] not assigned to an exact location on the device" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key\[4\]" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[4] } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { key[4] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "keydown Global clock in PIN 17 " "Info: Automatically promoted signal \"keydown\" to use Global clock in PIN 17" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "reduce_nor~1622 Global clock " "Info: Automatically promoted signal \"reduce_nor~1622\" to use Global clock" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~1622" } } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { reduce_nor~1622 } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" { Floorplan "D:/eda设计/VHDL/闹钟设计/time_lock.fld" "" "" { reduce_nor~1622 } "NODE_NAME" } }  } 0}