time_lock.map.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 21:54:09 2008 " "Info: Processing started: Sun Mar 02 21:54:09 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off time_lock -c time_lock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off time_lock -c time_lock" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fq_divider.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fq_divider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fq_divider-one " "Info: Found design unit 1: fq_divider-one" {  } { { "fq_divider.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/fq_divider.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fq_divider " "Info: Found entity 1: fq_divider" {  } { { "fq_divider.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/fq_divider.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file key_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 key_control-one " "Info: Found design unit 1: key_control-one" {  } { { "key_control.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/key_control.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 key_control " "Info: Found entity 1: key_control" {  } { { "key_control.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/key_control.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "state_control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file state_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 state_control-one " "Info: Found design unit 1: state_control-one" {  } { { "state_control.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/state_control.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 state_control " "Info: Found entity 1: state_control" {  } { { "state_control.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/state_control.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "time_lock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file time_lock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 time_lock-one " "Info: Found design unit 1: time_lock-one" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 time_lock " "Info: Found entity 1: time_lock" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "time_lock " "Info: Elaborating entity \"time_lock\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "s1 time_lock.vhd(14) " "Warning: VHDL Process Statement warning at time_lock.vhd(14): signal or variable \"s1\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"s1\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "lock_time0 time_lock.vhd(39) " "Warning: VHDL Process Statement warning at time_lock.vhd(39): signal \"lock_time0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 39 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "s1\[0\] " "Warning: Latch s1\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA key\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal key\[8\]" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } }  } 0}  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "s1\[1\] " "Warning: Latch s1\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA key\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal key\[8\]" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } }  } 0}  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "s1\[2\] " "Warning: Latch s1\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA key\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal key\[8\]" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } }  } 0}  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "s1\[3\] " "Warning: Latch s1\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA key\[8\] " "Warning: Ports D and ENA on the latch are fed by the same signal key\[8\]" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } }  } 0}  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "71 " "Info: Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "43 " "Info: Implemented 43 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 21:54:12 2008 " "Info: Processing ended: Sun Mar 02 21:54:12 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}