time_lock.tan.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计

{ "Info" "ITDB_TSU_RESULT" "lock_time0\[1\] key\[3\] keydown 10.274 ns register " "Info: tsu for register \"lock_time0\[1\]\" (data pin = \"key\[3\]\", clock pin = \"keydown\") is 10.274 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.344 ns + Longest pin register " "Info: + Longest pin to register delay is 12.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns key\[3\] 1 PIN PIN_10 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; PIN Node = 'key\[3\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { key[3] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.652 ns) + CELL(0.340 ns) 6.122 ns reduce_nor~1615 2 COMB LC_X4_Y2_N5 3 " "Info: 2: + IC(4.652 ns) + CELL(0.340 ns) = 6.122 ns; Loc. = LC_X4_Y2_N5; Fanout = 3; COMB Node = 'reduce_nor~1615'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "4.992 ns" { key[3] reduce_nor~1615 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 6.350 ns reduce_nor~1624 3 COMB LC_X4_Y2_N6 2 " "Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 6.350 ns; Loc. = LC_X4_Y2_N6; Fanout = 2; COMB Node = 'reduce_nor~1624'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.228 ns" { reduce_nor~1615 reduce_nor~1624 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.513 ns) + CELL(0.340 ns) 7.203 ns reduce_nor~1620 4 COMB LC_X4_Y2_N3 1 " "Info: 4: + IC(0.513 ns) + CELL(0.340 ns) = 7.203 ns; Loc. = LC_X4_Y2_N3; Fanout = 1; COMB Node = 'reduce_nor~1620'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.853 ns" { reduce_nor~1624 reduce_nor~1620 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.225 ns) 8.286 ns reduce_nor~1622 5 COMB LC_X6_Y2_N1 8 " "Info: 5: + IC(0.858 ns) + CELL(0.225 ns) = 8.286 ns; Loc. = LC_X6_Y2_N1; Fanout = 8; COMB Node = 'reduce_nor~1622'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "1.083 ns" { reduce_nor~1620 reduce_nor~1622 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.944 ns) 12.230 ns s1\[1\] 6 COMB LOOP LC_X2_Y2_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(3.944 ns) = 12.230 ns; Loc. = LC_X2_Y2_N1; Fanout = 2; COMB LOOP Node = 's1\[1\]'" { { "Info" "ITDB_PART_OF_SCC" "s1\[1\] LC_X2_Y2_N1 " "Info: Loc. = LC_X2_Y2_N1; Node \"s1\[1\]\"" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { s1[1] } "NODE_NAME" } "" } }  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { s1[1] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "3.944 ns" { reduce_nor~1622 s1[1] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.114 ns) 12.344 ns lock_time0\[1\] 7 REG LC_X2_Y2_N1 2 " "Info: 7: + IC(0.000 ns) + CELL(0.114 ns) = 12.344 ns; Loc. = LC_X2_Y2_N1; Fanout = 2; REG Node = 'lock_time0\[1\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.114 ns" { s1[1] lock_time0[1] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.181 ns 50.07 % " "Info: Total cell delay = 6.181 ns ( 50.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.163 ns 49.93 % " "Info: Total interconnect delay = 6.163 ns ( 49.93 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "12.344 ns" { key[3] reduce_nor~1615 reduce_nor~1624 reduce_nor~1620 reduce_nor~1622 s1[1] lock_time0[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "12.344 ns" { key[3] key[3]~out0 reduce_nor~1615 reduce_nor~1624 reduce_nor~1620 reduce_nor~1622 s1[1] lock_time0[1] } { 0.000ns 0.000ns 4.652ns 0.140ns 0.513ns 0.858ns 0.000ns 0.000ns } { 0.000ns 1.130ns 0.340ns 0.088ns 0.340ns 0.225ns 3.944ns 0.114ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keydown destination 2.099 ns - Shortest register " "Info: - Shortest clock path from clock \"keydown\" to destination register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns keydown 1 CLK PIN_17 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { keydown } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns lock_time0\[1\] 2 REG LC_X2_Y2_N1 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N1; Fanout = 2; REG Node = 'lock_time0\[1\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.969 ns" { keydown lock_time0[1] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[1] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "12.344 ns" { key[3] reduce_nor~1615 reduce_nor~1624 reduce_nor~1620 reduce_nor~1622 s1[1] lock_time0[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "12.344 ns" { key[3] key[3]~out0 reduce_nor~1615 reduce_nor~1624 reduce_nor~1620 reduce_nor~1622 s1[1] lock_time0[1] } { 0.000ns 0.000ns 4.652ns 0.140ns 0.513ns 0.858ns 0.000ns 0.000ns } { 0.000ns 1.130ns 0.340ns 0.088ns 0.340ns 0.225ns 3.944ns 0.114ns } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[1] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "keydown lock_time\[0\] lock_time0\[0\] 5.837 ns register " "Info: tco from clock \"keydown\" to destination pin \"lock_time\[0\]\" through register \"lock_time0\[0\]\" is 5.837 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keydown source 2.099 ns + Longest register " "Info: + Longest clock path from clock \"keydown\" to source register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns keydown 1 CLK PIN_17 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { keydown } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns lock_time0\[0\] 2 REG LC_X4_Y1_N7 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X4_Y1_N7; Fanout = 2; REG Node = 'lock_time0\[0\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.969 ns" { keydown lock_time0[0] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[0] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.565 ns + Longest register pin " "Info: + Longest register to pin delay is 3.565 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lock_time0\[0\] 1 REG LC_X4_Y1_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N7; Fanout = 2; REG Node = 'lock_time0\[0\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time0[0] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(1.622 ns) 3.565 ns lock_time\[0\] 2 PIN PIN_142 0 " "Info: 2: + IC(1.943 ns) + CELL(1.622 ns) = 3.565 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'lock_time\[0\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "3.565 ns" { lock_time0[0] lock_time[0] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 45.50 % " "Info: Total cell delay = 1.622 ns ( 45.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.943 ns 54.50 % " "Info: Total interconnect delay = 1.943 ns ( 54.50 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "3.565 ns" { lock_time0[0] lock_time[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.565 ns" { lock_time0[0] lock_time[0] } { 0.000ns 1.943ns } { 0.000ns 1.622ns } } }  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[0] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "3.565 ns" { lock_time0[0] lock_time[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.565 ns" { lock_time0[0] lock_time[0] } { 0.000ns 1.943ns } { 0.000ns 1.622ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lock_time0\[4\] reset keydown -3.543 ns register " "Info: th for register \"lock_time0\[4\]\" (data pin = \"reset\", clock pin = \"keydown\") is -3.543 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keydown destination 2.099 ns + Longest register " "Info: + Longest clock path from clock \"keydown\" to destination register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns keydown 1 CLK PIN_17 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { keydown } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns lock_time0\[4\] 2 REG LC_X4_Y1_N8 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X4_Y1_N8; Fanout = 2; REG Node = 'lock_time0\[4\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.969 ns" { keydown lock_time0[4] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[4] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[4] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.654 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns reset 1 PIN PIN_36 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_36; Fanout = 16; PIN Node = 'reset'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { reset } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.857 ns) + CELL(0.667 ns) 5.654 ns lock_time0\[4\] 2 REG LC_X4_Y1_N8 2 " "Info: 2: + IC(3.857 ns) + CELL(0.667 ns) = 5.654 ns; Loc. = LC_X4_Y1_N8; Fanout = 2; REG Node = 'lock_time0\[4\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "4.524 ns" { reset lock_time0[4] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.797 ns 31.78 % " "Info: Total cell delay = 1.797 ns ( 31.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.857 ns 68.22 % " "Info: Total interconnect delay = 3.857 ns ( 68.22 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "5.654 ns" { reset lock_time0[4] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "5.654 ns" { reset reset~out0 lock_time0[4] } { 0.000ns 0.000ns 3.857ns } { 0.000ns 1.130ns 0.667ns } } }  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[4] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[4] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "5.654 ns" { reset lock_time0[4] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "5.654 ns" { reset reset~out0 lock_time0[4] } { 0.000ns 0.000ns 3.857ns } { 0.000ns 1.130ns 0.667ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 21:54:29 2008 " "Info: Processing ended: Sun Mar 02 21:54:29 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}