time_lock.tan.qmsg

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "s1\[2\] " "Info: Node \"s1\[2\]\"" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "s1\[1\] " "Info: Node \"s1\[1\]\"" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "s1\[0\] " "Info: Node \"s1\[0\]\"" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "keydown " "Info: Assuming node \"keydown\" is an undefined clock" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keydown" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "keydown register register lock_time0\[2\] lock_time0\[6\] 405.19 MHz Internal " "Info: Clock \"keydown\" Internal fmax is restricted to 405.19 MHz between source register \"lock_time0\[2\]\" and destination register \"lock_time0\[6\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.099 ns + Longest register register " "Info: + Longest register to register delay is 1.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lock_time0\[2\] 1 REG LC_X2_Y2_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y2_N3; Fanout = 2; REG Node = 'lock_time0\[2\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time0[2] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.238 ns) 1.099 ns lock_time0\[6\] 2 REG LC_X2_Y2_N9 2 " "Info: 2: + IC(0.861 ns) + CELL(0.238 ns) = 1.099 ns; Loc. = LC_X2_Y2_N9; Fanout = 2; REG Node = 'lock_time0\[6\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "1.099 ns" { lock_time0[2] lock_time0[6] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.238 ns 21.66 % " "Info: Total cell delay = 0.238 ns ( 21.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.861 ns 78.34 % " "Info: Total interconnect delay = 0.861 ns ( 78.34 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "1.099 ns" { lock_time0[2] lock_time0[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.099 ns" { lock_time0[2] lock_time0[6] } { 0.000ns 0.861ns } { 0.000ns 0.238ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keydown destination 2.099 ns + Shortest register " "Info: + Shortest clock path from clock \"keydown\" to destination register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns keydown 1 CLK PIN_17 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { keydown } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns lock_time0\[6\] 2 REG LC_X2_Y2_N9 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N9; Fanout = 2; REG Node = 'lock_time0\[6\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.969 ns" { keydown lock_time0[6] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[6] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keydown source 2.099 ns - Longest register " "Info: - Longest clock path from clock \"keydown\" to source register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns keydown 1 CLK PIN_17 16 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { keydown } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns lock_time0\[2\] 2 REG LC_X2_Y2_N3 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N3; Fanout = 2; REG Node = 'lock_time0\[2\]'" {  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "0.969 ns" { keydown lock_time0[2] } "NODE_NAME" } "" } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[2] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[6] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[2] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "1.099 ns" { lock_time0[2] lock_time0[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.099 ns" { lock_time0[2] lock_time0[6] } { 0.000ns 0.861ns } { 0.000ns 0.238ns } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[6] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "2.099 ns" { keydown lock_time0[2] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { keydown keydown~out0 lock_time0[2] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" "" { Report "D:/eda设计/VHDL/闹钟设计/db/time_lock_cmp.qrpt" Compiler "time_lock" "UNKNOWN" "V1" "D:/eda设计/VHDL/闹钟设计/db/time_lock.quartus_db" { Floorplan "D:/eda设计/VHDL/闹钟设计/" "" "" { lock_time0[6] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { lock_time0[6] } {  } {  } } } { "time_lock.vhd" "" { Text "D:/eda设计/VHDL/闹钟设计/time_lock.vhd" 12 -1 0 } }  } 0}