time_lock.vhd

来自「软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
----------------------------
entity time_lock is
port(reset,keydown:in std_logic;
	key:in std_logic_vector(9 downto 0);
	lock_time:out std_logic_vector(15 downto 0));
end entity time_lock;
----------------------------
architecture one of time_lock is
signal s1:std_logic_vector(3 downto 0);
signal lock_time0:std_logic_vector(15 downto 0);
begin
p1:process(key)
begin
	case key is
	when "0000000001" =>s1<="0000";		--0
	when "0000000010" =>s1<="0001";		--1
	when "0000000100" =>s1<="0010";		--2
	when "0000001000" =>s1<="0011";		--3
	when "0000010000" =>s1<="0100";		--4
	when "0000100000" =>s1<="0101";		--5
	when "0001000000" =>s1<="0110";		--6
	when "0010000000" =>s1<="0111";		--7
	when "0100000000" =>s1<="1000";		--8
	when "1000000000" =>s1<="1001";		--9
	when others =>null;
	end case;
end process p1;
p2:process(s1,reset,key,keydown)
begin
	if reset='1' then lock_time<=(others=>'0');
	elsif keydown'event and keydown='1' then
		lock_time0(15 downto 12)<=lock_time0(11 downto 8);
		lock_time0(11 downto 8)<=lock_time0(7 downto 4);
		lock_time0(7 downto 4)<=lock_time0(3 downto 0);
		lock_time0(3 downto 0)<=s1;
	end if;
	lock_time<=lock_time0;
end process p2;
end architecture;