fq_divider.fit.rpt

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计

Fitter report for fq_divider
Sun Mar 02 21:48:19 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Failed - Sun Mar 02 21:48:19 2008        ;
; Quartus II Version    ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name         ; fq_divider                               ;
; Top-level Entity Name ; time_lock                                ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C3T144C6                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 43                                       ;
; Total pins            ; 28                                       ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0                                        ;
; Total PLLs            ; 0                                        ;
+-----------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C3T144C6                    ;                                ;
; Use smart compilation                              ; Off                            ; Off                            ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+---------------------------------------------------------------+
; Fitter Device Options                                         ;
+----------------------------------------------+----------------+
; Option                                       ; Setting        ;
+----------------------------------------------+----------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off            ;
; Enable device-wide reset (DEV_CLRn)          ; Off            ;
; Enable device-wide output enable (DEV_OE)    ; Off            ;
; Enable INIT_DONE output                      ; Off            ;
; Configuration scheme                         ; Passive Serial ;
; Error detection CRC                          ; Off            ;
; Base pin-out file on sameframe device        ; Off            ;
+----------------------------------------------+----------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Mar 02 21:48:19 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fq_divider -c fq_divider
Warning: FLEXlm software error: Future license file format or misspelling in license file  The file was issued for a later version of FLEXlm than this  program understands. Feature:       quartus License path:  E:/altera/quartus50/bin/SO1.dat FLEXlm error:  -90,313 For further information, refer to the FLEXlm End User Manual, available at "www.macrovision.com".
Error: Current license file does not support the EP1C3T144C6 device
Error: Quartus II Fitter was unsuccessful. 1 error, 1 warning
    Error: Processing ended: Sun Mar 02 21:48:19 2008
    Error: Elapsed time: 00:00:01