📄 time_lock.tan.rpt
字号:
; N/A ; None ; 5.837 ns ; lock_time0[0] ; lock_time[0] ; keydown ;
; N/A ; None ; 5.722 ns ; lock_time0[4] ; lock_time[4] ; keydown ;
; N/A ; None ; 5.611 ns ; lock_time0[2] ; lock_time[2] ; keydown ;
; N/A ; None ; 5.421 ns ; lock_time0[7] ; lock_time[7] ; keydown ;
; N/A ; None ; 5.380 ns ; lock_time0[12] ; lock_time[12] ; keydown ;
; N/A ; None ; 5.303 ns ; lock_time0[5] ; lock_time[5] ; keydown ;
; N/A ; None ; 5.289 ns ; lock_time0[9] ; lock_time[9] ; keydown ;
; N/A ; None ; 5.280 ns ; lock_time0[1] ; lock_time[1] ; keydown ;
; N/A ; None ; 5.275 ns ; lock_time0[14] ; lock_time[14] ; keydown ;
; N/A ; None ; 5.262 ns ; lock_time0[13] ; lock_time[13] ; keydown ;
; N/A ; None ; 5.179 ns ; lock_time0[15] ; lock_time[15] ; keydown ;
; N/A ; None ; 5.179 ns ; lock_time0[3] ; lock_time[3] ; keydown ;
; N/A ; None ; 5.172 ns ; lock_time0[11] ; lock_time[11] ; keydown ;
; N/A ; None ; 5.018 ns ; lock_time0[6] ; lock_time[6] ; keydown ;
; N/A ; None ; 4.989 ns ; lock_time0[10] ; lock_time[10] ; keydown ;
; N/A ; None ; 4.888 ns ; lock_time0[8] ; lock_time[8] ; keydown ;
+-------+--------------+------------+----------------+---------------+------------+
+------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+--------+----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+--------+----------------+----------+
; N/A ; None ; -3.543 ns ; reset ; lock_time0[4] ; keydown ;
; N/A ; None ; -3.543 ns ; reset ; lock_time0[0] ; keydown ;
; N/A ; None ; -3.543 ns ; reset ; lock_time0[8] ; keydown ;
; N/A ; None ; -3.543 ns ; reset ; lock_time0[12] ; keydown ;
; N/A ; None ; -3.877 ns ; reset ; lock_time0[5] ; keydown ;
; N/A ; None ; -3.877 ns ; reset ; lock_time0[1] ; keydown ;
; N/A ; None ; -3.877 ns ; reset ; lock_time0[6] ; keydown ;
; N/A ; None ; -3.877 ns ; reset ; lock_time0[2] ; keydown ;
; N/A ; None ; -3.877 ns ; reset ; lock_time0[9] ; keydown ;
; N/A ; None ; -3.877 ns ; reset ; lock_time0[10] ; keydown ;
; N/A ; None ; -3.877 ns ; reset ; lock_time0[13] ; keydown ;
; N/A ; None ; -3.877 ns ; reset ; lock_time0[14] ; keydown ;
; N/A ; None ; -3.885 ns ; key[8] ; lock_time0[3] ; keydown ;
; N/A ; None ; -3.928 ns ; key[5] ; lock_time0[3] ; keydown ;
; N/A ; None ; -4.070 ns ; key[7] ; lock_time0[0] ; keydown ;
; N/A ; None ; -4.080 ns ; key[9] ; lock_time0[2] ; keydown ;
; N/A ; None ; -4.125 ns ; reset ; lock_time0[7] ; keydown ;
; N/A ; None ; -4.125 ns ; reset ; lock_time0[3] ; keydown ;
; N/A ; None ; -4.125 ns ; reset ; lock_time0[11] ; keydown ;
; N/A ; None ; -4.125 ns ; reset ; lock_time0[15] ; keydown ;
; N/A ; None ; -4.177 ns ; key[6] ; lock_time0[3] ; keydown ;
; N/A ; None ; -4.384 ns ; key[9] ; lock_time0[3] ; keydown ;
; N/A ; None ; -4.384 ns ; key[7] ; lock_time0[3] ; keydown ;
; N/A ; None ; -4.388 ns ; key[4] ; lock_time0[2] ; keydown ;
; N/A ; None ; -4.411 ns ; key[0] ; lock_time0[3] ; keydown ;
; N/A ; None ; -4.424 ns ; key[6] ; lock_time0[0] ; keydown ;
; N/A ; None ; -4.526 ns ; key[2] ; lock_time0[0] ; keydown ;
; N/A ; None ; -4.593 ns ; key[4] ; lock_time0[3] ; keydown ;
; N/A ; None ; -4.683 ns ; key[4] ; lock_time0[0] ; keydown ;
; N/A ; None ; -4.770 ns ; key[5] ; lock_time0[2] ; keydown ;
; N/A ; None ; -5.039 ns ; key[8] ; lock_time0[0] ; keydown ;
; N/A ; None ; -5.087 ns ; key[2] ; lock_time0[3] ; keydown ;
; N/A ; None ; -5.146 ns ; key[5] ; lock_time0[0] ; keydown ;
; N/A ; None ; -5.200 ns ; key[9] ; lock_time0[0] ; keydown ;
; N/A ; None ; -5.298 ns ; key[2] ; lock_time0[2] ; keydown ;
; N/A ; None ; -5.382 ns ; key[9] ; lock_time0[1] ; keydown ;
; N/A ; None ; -5.414 ns ; key[0] ; lock_time0[0] ; keydown ;
; N/A ; None ; -5.568 ns ; key[8] ; lock_time0[1] ; keydown ;
; N/A ; None ; -5.592 ns ; key[7] ; lock_time0[1] ; keydown ;
; N/A ; None ; -5.646 ns ; key[8] ; lock_time0[2] ; keydown ;
; N/A ; None ; -5.670 ns ; key[7] ; lock_time0[2] ; keydown ;
; N/A ; None ; -5.672 ns ; key[1] ; lock_time0[3] ; keydown ;
; N/A ; None ; -5.724 ns ; key[2] ; lock_time0[1] ; keydown ;
; N/A ; None ; -5.727 ns ; key[6] ; lock_time0[1] ; keydown ;
; N/A ; None ; -5.780 ns ; key[1] ; lock_time0[0] ; keydown ;
; N/A ; None ; -5.805 ns ; key[6] ; lock_time0[2] ; keydown ;
; N/A ; None ; -5.883 ns ; key[1] ; lock_time0[2] ; keydown ;
; N/A ; None ; -5.943 ns ; key[0] ; lock_time0[1] ; keydown ;
; N/A ; None ; -6.021 ns ; key[0] ; lock_time0[2] ; keydown ;
; N/A ; None ; -6.025 ns ; key[3] ; lock_time0[3] ; keydown ;
; N/A ; None ; -6.134 ns ; key[3] ; lock_time0[0] ; keydown ;
; N/A ; None ; -6.236 ns ; key[3] ; lock_time0[2] ; keydown ;
; N/A ; None ; -6.305 ns ; key[1] ; lock_time0[1] ; keydown ;
; N/A ; None ; -6.509 ns ; key[4] ; lock_time0[1] ; keydown ;
; N/A ; None ; -6.608 ns ; key[5] ; lock_time0[1] ; keydown ;
; N/A ; None ; -6.655 ns ; key[3] ; lock_time0[1] ; keydown ;
+---------------+-------------+-----------+--------+----------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sun Mar 02 21:54:28 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off time_lock -c time_lock --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
Warning: Node "s1[0]" is a latch
Warning: Node "s1[1]" is a latch
Warning: Node "s1[2]" is a latch
Warning: Node "s1[3]" is a latch
Info: Found combinational loop of 1 nodes
Info: Node "s1[3]"
Info: Found combinational loop of 1 nodes
Info: Node "s1[2]"
Info: Found combinational loop of 1 nodes
Info: Node "s1[1]"
Info: Found combinational loop of 1 nodes
Info: Node "s1[0]"
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "keydown" is an undefined clock
Info: Clock "keydown" Internal fmax is restricted to 405.19 MHz between source register "lock_time0[2]" and destination register "lock_time0[6]"
Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.099 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y2_N3; Fanout = 2; REG Node = 'lock_time0[2]'
Info: 2: + IC(0.861 ns) + CELL(0.238 ns) = 1.099 ns; Loc. = LC_X2_Y2_N9; Fanout = 2; REG Node = 'lock_time0[6]'
Info: Total cell delay = 0.238 ns ( 21.66 % )
Info: Total interconnect delay = 0.861 ns ( 78.34 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "keydown" to destination register is 2.099 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'
Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N9; Fanout = 2; REG Node = 'lock_time0[6]'
Info: Total cell delay = 1.677 ns ( 79.90 % )
Info: Total interconnect delay = 0.422 ns ( 20.10 % )
Info: - Longest clock path from clock "keydown" to source register is 2.099 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'
Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N3; Fanout = 2; REG Node = 'lock_time0[2]'
Info: Total cell delay = 1.677 ns ( 79.90 % )
Info: Total interconnect delay = 0.422 ns ( 20.10 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "lock_time0[1]" (data pin = "key[3]", clock pin = "keydown") is 10.274 ns
Info: + Longest pin to register delay is 12.344 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; PIN Node = 'key[3]'
Info: 2: + IC(4.652 ns) + CELL(0.340 ns) = 6.122 ns; Loc. = LC_X4_Y2_N5; Fanout = 3; COMB Node = 'reduce_nor~1615'
Info: 3: + IC(0.140 ns) + CELL(0.088 ns) = 6.350 ns; Loc. = LC_X4_Y2_N6; Fanout = 2; COMB Node = 'reduce_nor~1624'
Info: 4: + IC(0.513 ns) + CELL(0.340 ns) = 7.203 ns; Loc. = LC_X4_Y2_N3; Fanout = 1; COMB Node = 'reduce_nor~1620'
Info: 5: + IC(0.858 ns) + CELL(0.225 ns) = 8.286 ns; Loc. = LC_X6_Y2_N1; Fanout = 8; COMB Node = 'reduce_nor~1622'
Info: 6: + IC(0.000 ns) + CELL(3.944 ns) = 12.230 ns; Loc. = LC_X2_Y2_N1; Fanout = 2; COMB LOOP Node = 's1[1]'
Info: Loc. = LC_X2_Y2_N1; Node "s1[1]"
Info: 7: + IC(0.000 ns) + CELL(0.114 ns) = 12.344 ns; Loc. = LC_X2_Y2_N1; Fanout = 2; REG Node = 'lock_time0[1]'
Info: Total cell delay = 6.181 ns ( 50.07 % )
Info: Total interconnect delay = 6.163 ns ( 49.93 % )
Info: + Micro setup delay of destination is 0.029 ns
Info: - Shortest clock path from clock "keydown" to destination register is 2.099 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'
Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N1; Fanout = 2; REG Node = 'lock_time0[1]'
Info: Total cell delay = 1.677 ns ( 79.90 % )
Info: Total interconnect delay = 0.422 ns ( 20.10 % )
Info: tco from clock "keydown" to destination pin "lock_time[0]" through register "lock_time0[0]" is 5.837 ns
Info: + Longest clock path from clock "keydown" to source register is 2.099 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'
Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X4_Y1_N7; Fanout = 2; REG Node = 'lock_time0[0]'
Info: Total cell delay = 1.677 ns ( 79.90 % )
Info: Total interconnect delay = 0.422 ns ( 20.10 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Longest register to pin delay is 3.565 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N7; Fanout = 2; REG Node = 'lock_time0[0]'
Info: 2: + IC(1.943 ns) + CELL(1.622 ns) = 3.565 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'lock_time[0]'
Info: Total cell delay = 1.622 ns ( 45.50 % )
Info: Total interconnect delay = 1.943 ns ( 54.50 % )
Info: th for register "lock_time0[4]" (data pin = "reset", clock pin = "keydown") is -3.543 ns
Info: + Longest clock path from clock "keydown" to destination register is 2.099 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 16; CLK Node = 'keydown'
Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X4_Y1_N8; Fanout = 2; REG Node = 'lock_time0[4]'
Info: Total cell delay = 1.677 ns ( 79.90 % )
Info: Total interconnect delay = 0.422 ns ( 20.10 % )
Info: + Micro hold delay of destination is 0.012 ns
Info: - Shortest pin to register delay is 5.654 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_36; Fanout = 16; PIN Node = 'reset'
Info: 2: + IC(3.857 ns) + CELL(0.667 ns) = 5.654 ns; Loc. = LC_X4_Y1_N8; Fanout = 2; REG Node = 'lock_time0[4]'
Info: Total cell delay = 1.797 ns ( 31.78 % )
Info: Total interconnect delay = 3.857 ns ( 68.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 6 warnings
Info: Processing ended: Sun Mar 02 21:54:29 2008
Info: Elapsed time: 00:00:01
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