fq_divider.map.summary

来自「软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Sun Mar 02 21:48:17 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : fq_divider
Top-level Entity Name : time_lock
Family : Cyclone
Device : EP1C3T144C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 43
Total pins : 28
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0