fq_divider.map.rpt

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计

; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path           ;
+----------------------------------+-----------------+-----------------+----------------------------------------+
; time_lock.vhd                    ; yes             ; User VHDL File  ; D:/eda设计/VHDL/闹钟设计/time_lock.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 43        ;
; Total combinational functions   ; 27        ;
;     -- Total 4-input functions  ; 17        ;
;     -- Total 3-input functions  ; 8         ;
;     -- Total 2-input functions  ; 2         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 16        ;
; I/O pins                        ; 28        ;
; Maximum fan-out node            ; keydown   ;
; Maximum fan-out                 ; 16        ;
; Total fan-out                   ; 160       ;
; Average fan-out                 ; 2.25      ;
+---------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |time_lock                 ; 43 (43)     ; 16           ; 0           ; 28   ; 0            ; 27 (27)      ; 16 (16)           ; 0 (0)            ; 0 (0)           ; |time_lock          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; s1[0]                                         ;   ;
; s1[1]                                         ;   ;
; s1[2]                                         ;   ;
; s1[3]                                         ;   ;
; Number of user-specified and inferred latches ; 4 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 16    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 16    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/eda设计/VHDL/闹钟设计/fq_divider.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Mar 02 21:48:13 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fq_divider -c fq_divider
Info: Found 2 design units, including 1 entities, in source file fq_divider.vhd
    Info: Found design unit 1: fq_divider-one
    Info: Found entity 1: fq_divider
Info: Found 2 design units, including 1 entities, in source file key_control.vhd
    Info: Found design unit 1: key_control-one
    Info: Found entity 1: key_control
Info: Found 2 design units, including 1 entities, in source file state_control.vhd
    Info: Found design unit 1: state_control-one
    Info: Found entity 1: state_control
Info: Found 2 design units, including 1 entities, in source file time_lock.vhd
    Info: Found design unit 1: time_lock-one
    Info: Found entity 1: time_lock
Info: Elaborating entity "time_lock" for the top level hierarchy
Warning: VHDL Process Statement warning at time_lock.vhd(14): signal or variable "s1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "s1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at time_lock.vhd(39): signal "lock_time0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Latch s1[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal key[8]
Warning: Latch s1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal key[8]
Warning: Latch s1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal key[8]
Warning: Latch s1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal key[8]
Info: Implemented 71 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 16 output pins
    Info: Implemented 43 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Sun Mar 02 21:48:17 2008
    Info: Elapsed time: 00:00:05