clock.tan.qmsg

数字电子钟的Verilog HDL语言描述。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_1k " "Info: Detected ripple clock \"clk_1k\" as buffer" {  } { { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 23 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_1k" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_1hz " "Info: Detected ripple clock \"clk_1hz\" as buffer" {  } { { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 47 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_100M register count1\[16\] register clk_1k 73.64 MHz 13.58 ns Internal " "Info: Clock \"clk_100M\" has Internal fmax of 73.64 MHz between source register \"count1\[16\]\" and destination register \"clk_1k\" (period= 13.58 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.081 ns + Longest register register " "Info: + Longest register to register delay is 6.081 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count1\[16\] 1 REG LC_X6_Y6_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y6_N9; Fanout = 4; REG Node = 'count1\[16\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count1[16] } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.740 ns) 2.640 ns Equal1~199 2 COMB LC_X10_Y6_N2 1 " "Info: 2: + IC(1.900 ns) + CELL(0.740 ns) = 2.640 ns; Loc. = LC_X10_Y6_N2; Fanout = 1; COMB Node = 'Equal1~199'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.640 ns" { count1[16] Equal1~199 } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.914 ns) 4.709 ns Equal1~202 3 COMB LC_X10_Y6_N1 7 " "Info: 3: + IC(1.155 ns) + CELL(0.914 ns) = 4.709 ns; Loc. = LC_X10_Y6_N1; Fanout = 7; COMB Node = 'Equal1~202'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.069 ns" { Equal1~199 Equal1~202 } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.781 ns) + CELL(0.591 ns) 6.081 ns clk_1k 4 REG LC_X10_Y6_N3 11 " "Info: 4: + IC(0.781 ns) + CELL(0.591 ns) = 6.081 ns; Loc. = LC_X10_Y6_N3; Fanout = 11; REG Node = 'clk_1k'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.372 ns" { Equal1~202 clk_1k } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.245 ns ( 36.92 % ) " "Info: Total cell delay = 2.245 ns ( 36.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.836 ns ( 63.08 % ) " "Info: Total interconnect delay = 3.836 ns ( 63.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.081 ns" { count1[16] Equal1~199 Equal1~202 clk_1k } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.081 ns" { count1[16] Equal1~199 Equal1~202 clk_1k } { 0.000ns 1.900ns 1.155ns 0.781ns } { 0.000ns 0.740ns 0.914ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_100M destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_100M\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_100M 1 CLK PIN_18 44 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 44; CLK Node = 'clk_100M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_100M } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns clk_1k 2 REG LC_X10_Y6_N3 11 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X10_Y6_N3; Fanout = 11; REG Node = 'clk_1k'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { clk_100M clk_1k } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk_100M clk_1k } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk_100M clk_100M~combout clk_1k } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_100M source 3.681 ns - Longest register " "Info: - Longest clock path from clock \"clk_100M\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_100M 1 CLK PIN_18 44 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 44; CLK Node = 'clk_100M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_100M } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns count1\[16\] 2 REG LC_X6_Y6_N9 4 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X6_Y6_N9; Fanout = 4; REG Node = 'count1\[16\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { clk_100M count1[16] } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk_100M count1[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk_100M clk_100M~combout count1[16] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk_100M clk_1k } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk_100M clk_100M~combout clk_1k } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk_100M count1[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk_100M clk_100M~combout count1[16] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 56 -1 0 } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 23 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.081 ns" { count1[16] Equal1~199 Equal1~202 clk_1k } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.081 ns" { count1[16] Equal1~199 Equal1~202 clk_1k } { 0.000ns 1.900ns 1.155ns 0.781ns } { 0.000ns 0.740ns 0.914ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk_100M clk_1k } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk_100M clk_100M~combout clk_1k } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { clk_100M count1[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { clk_100M clk_100M~combout count1[16] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_100M out_data\[2\] led_buf\[1\] 15.083 ns register " "Info: tco from clock \"clk_100M\" to destination pin \"out_data\[2\]\" through register \"led_buf\[1\]\" is 15.083 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_100M source 8.715 ns + Longest register " "Info: + Longest clock path from clock \"clk_100M\" to source register is 8.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_100M 1 CLK PIN_18 44 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 44; CLK Node = 'clk_100M'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_100M } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clk_1k 2 REG LC_X10_Y6_N3 11 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X10_Y6_N3; Fanout = 11; REG Node = 'clk_1k'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.894 ns" { clk_100M clk_1k } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.740 ns) + CELL(0.918 ns) 8.715 ns led_buf\[1\] 3 REG LC_X7_Y7_N4 7 " "Info: 3: + IC(3.740 ns) + CELL(0.918 ns) = 8.715 ns; Loc. = LC_X7_Y7_N4; Fanout = 7; REG Node = 'led_buf\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.658 ns" { clk_1k led_buf[1] } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 38.73 % ) " "Info: Total cell delay = 3.375 ns ( 38.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.340 ns ( 61.27 % ) " "Info: Total interconnect delay = 5.340 ns ( 61.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.715 ns" { clk_100M clk_1k led_buf[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.715 ns" { clk_100M clk_100M~combout clk_1k led_buf[1] } { 0.000ns 0.000ns 1.600ns 3.740ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 114 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.992 ns + Longest register pin " "Info: + Longest register to pin delay is 5.992 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_buf\[1\] 1 REG LC_X7_Y7_N4 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y7_N4; Fanout = 7; REG Node = 'led_buf\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { led_buf[1] } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.914 ns) 1.961 ns WideOr4~15 2 COMB LC_X7_Y7_N7 1 " "Info: 2: + IC(1.047 ns) + CELL(0.914 ns) = 1.961 ns; Loc. = LC_X7_Y7_N7; Fanout = 1; COMB Node = 'WideOr4~15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.961 ns" { led_buf[1] WideOr4~15 } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.709 ns) + CELL(2.322 ns) 5.992 ns out_data\[2\] 3 PIN PIN_132 0 " "Info: 3: + IC(1.709 ns) + CELL(2.322 ns) = 5.992 ns; Loc. = PIN_132; Fanout = 0; PIN Node = 'out_data\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.031 ns" { WideOr4~15 out_data[2] } "NODE_NAME" } } { "clock.v" "" { Text "D:/altera/project/clock/clock.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 54.01 % ) " "Info: Total cell delay = 3.236 ns ( 54.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.756 ns ( 45.99 % ) " "Info: Total interconnect delay = 2.756 ns ( 45.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.992 ns" { led_buf[1] WideOr4~15 out_data[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.992 ns" { led_buf[1] WideOr4~15 out_data[2] } { 0.000ns 1.047ns 1.709ns } { 0.000ns 0.914ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.715 ns" { clk_100M clk_1k led_buf[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.715 ns" { clk_100M clk_100M~combout clk_1k led_buf[1] } { 0.000ns 0.000ns 1.600ns 3.740ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.992 ns" { led_buf[1] WideOr4~15 out_data[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.992 ns" { led_buf[1] WideOr4~15 out_data[2] } { 0.000ns 1.047ns 1.709ns } { 0.000ns 0.914ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 05 19:28:06 2009 " "Info: Processing ended: Thu Mar 05 19:28:06 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}