clock.fit.summary

数字电子钟的Verilog HDL语言描述。

Fitter Status : Successful - Thu Mar 05 19:28:00 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX II
Device : EPM570T144C5
Timing Models : Final
Total logic elements : 153 / 570 ( 27 % )
Total pins : 14 / 116 ( 12 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )