clock.tan.rpt

数字电子钟的Verilog HDL语言描述。

; N/A   ; None         ; 13.744 ns  ; led_buf[0]     ; out_data[1] ; clk_100M   ;
; N/A   ; None         ; 13.742 ns  ; led_buf[0]     ; out_data[5] ; clk_100M   ;
; N/A   ; None         ; 13.635 ns  ; led_buf[2]     ; out_data[4] ; clk_100M   ;
; N/A   ; None         ; 13.635 ns  ; led_buf[2]     ; out_data[3] ; clk_100M   ;
; N/A   ; None         ; 13.627 ns  ; led_buf[2]     ; out_data[1] ; clk_100M   ;
; N/A   ; None         ; 13.625 ns  ; led_buf[2]     ; out_data[5] ; clk_100M   ;
; N/A   ; None         ; 13.516 ns  ; led_buf[3]     ; out_data[6] ; clk_100M   ;
; N/A   ; None         ; 13.280 ns  ; out_sel_reg[0] ; out_sel[0]  ; clk_100M   ;
; N/A   ; None         ; 13.268 ns  ; out_sel_reg[3] ; out_sel[3]  ; clk_100M   ;
; N/A   ; None         ; 13.234 ns  ; led_buf[3]     ; out_data[4] ; clk_100M   ;
; N/A   ; None         ; 13.234 ns  ; led_buf[3]     ; out_data[3] ; clk_100M   ;
; N/A   ; None         ; 13.227 ns  ; led_buf[3]     ; out_data[1] ; clk_100M   ;
; N/A   ; None         ; 13.226 ns  ; led_buf[3]     ; out_data[5] ; clk_100M   ;
; N/A   ; None         ; 12.187 ns  ; out_sel_reg[1] ; out_sel[1]  ; clk_100M   ;
; N/A   ; None         ; 12.181 ns  ; out_sel_reg[2] ; out_sel[2]  ; clk_100M   ;
; N/A   ; None         ; 11.640 ns  ; clk_1hz        ; out_data[7] ; clk_100M   ;
; N/A   ; None         ; 9.301 ns   ; clk_1hz        ; clk_out     ; clk_100M   ;
+-------+--------------+------------+----------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Mar 05 19:28:05 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_100M" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk_1k" as buffer
    Info: Detected ripple clock "clk_1hz" as buffer
Info: Clock "clk_100M" has Internal fmax of 73.64 MHz between source register "count1[16]" and destination register "clk_1k" (period= 13.58 ns)
    Info: + Longest register to register delay is 6.081 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y6_N9; Fanout = 4; REG Node = 'count1[16]'
        Info: 2: + IC(1.900 ns) + CELL(0.740 ns) = 2.640 ns; Loc. = LC_X10_Y6_N2; Fanout = 1; COMB Node = 'Equal1~199'
        Info: 3: + IC(1.155 ns) + CELL(0.914 ns) = 4.709 ns; Loc. = LC_X10_Y6_N1; Fanout = 7; COMB Node = 'Equal1~202'
        Info: 4: + IC(0.781 ns) + CELL(0.591 ns) = 6.081 ns; Loc. = LC_X10_Y6_N3; Fanout = 11; REG Node = 'clk_1k'
        Info: Total cell delay = 2.245 ns ( 36.92 % )
        Info: Total interconnect delay = 3.836 ns ( 63.08 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk_100M" to destination register is 3.681 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 44; CLK Node = 'clk_100M'
            Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X10_Y6_N3; Fanout = 11; REG Node = 'clk_1k'
            Info: Total cell delay = 2.081 ns ( 56.53 % )
            Info: Total interconnect delay = 1.600 ns ( 43.47 % )
        Info: - Longest clock path from clock "clk_100M" to source register is 3.681 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 44; CLK Node = 'clk_100M'
            Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X6_Y6_N9; Fanout = 4; REG Node = 'count1[16]'
            Info: Total cell delay = 2.081 ns ( 56.53 % )
            Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tco from clock "clk_100M" to destination pin "out_data[2]" through register "led_buf[1]" is 15.083 ns
    Info: + Longest clock path from clock "clk_100M" to source register is 8.715 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 44; CLK Node = 'clk_100M'
        Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X10_Y6_N3; Fanout = 11; REG Node = 'clk_1k'
        Info: 3: + IC(3.740 ns) + CELL(0.918 ns) = 8.715 ns; Loc. = LC_X7_Y7_N4; Fanout = 7; REG Node = 'led_buf[1]'
        Info: Total cell delay = 3.375 ns ( 38.73 % )
        Info: Total interconnect delay = 5.340 ns ( 61.27 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 5.992 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y7_N4; Fanout = 7; REG Node = 'led_buf[1]'
        Info: 2: + IC(1.047 ns) + CELL(0.914 ns) = 1.961 ns; Loc. = LC_X7_Y7_N7; Fanout = 1; COMB Node = 'WideOr4~15'
        Info: 3: + IC(1.709 ns) + CELL(2.322 ns) = 5.992 ns; Loc. = PIN_132; Fanout = 0; PIN Node = 'out_data[2]'
        Info: Total cell delay = 3.236 ns ( 54.01 % )
        Info: Total interconnect delay = 2.756 ns ( 45.99 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Mar 05 19:28:06 2009
    Info: Elapsed time: 00:00:01