szsz.hier_info

该文件是用VHDL变成实现的数字钟程序

|hour
clk => hour1_t[3].CLK
clk => hour1_t[2].CLK
clk => hour1_t[1].CLK
clk => hour1_t[0].CLK
clk => hour2_t[3].CLK
clk => hour2_t[2].CLK
clk => hour2_t[1].CLK
clk => hour2_t[0].CLK
reset => hour1_t[3].ACLR
reset => hour1_t[2].ACLR
reset => hour1_t[1].ACLR
reset => hour1_t[0].ACLR
reset => hour2_t[3].ACLR
reset => hour2_t[2].ACLR
reset => hour2_t[1].ACLR
reset => hour2_t[0].ACLR
hour1[0] <= hour1_t[0].DB_MAX_OUTPUT_PORT_TYPE
hour1[1] <= hour1_t[1].DB_MAX_OUTPUT_PORT_TYPE
hour1[2] <= hour1_t[2].DB_MAX_OUTPUT_PORT_TYPE
hour1[3] <= hour1_t[3].DB_MAX_OUTPUT_PORT_TYPE
hour2[0] <= hour2_t[0].DB_MAX_OUTPUT_PORT_TYPE
hour2[1] <= hour2_t[1].DB_MAX_OUTPUT_PORT_TYPE
hour2[2] <= hour2_t[2].DB_MAX_OUTPUT_PORT_TYPE
hour2[3] <= hour2_t[3].DB_MAX_OUTPUT_PORT_TYPE