second.vhd

来自「该文件是用VHDL变成实现的数字钟程序」· VHDL 代码 · 共 37 行

library ieee; --miaojishu
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port(clk,reset:in std_logic;
     sec1,sec2:out std_logic_vector(3 downto 0);
     carry:out std_logic);
end;
architecture rt1 of second is
signal sec1_t,sec2_t:std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if reset='1' then
sec1_t<="0000";
sec2_t<="0000";
elsif clk'event and clk='1' then
if sec1_t="1001" then
   sec1_t<="0000";
if sec2_t="0101" then
   sec2_t<="0000";
else
sec2_t<=sec2_t+1;
end if;
else 
sec1_t<=sec1_t+1;
end if;
if sec1_t="1001" and sec2_t="0101" then
carry<='1';
else
carry<='0';
end if;
end if;
sec1<=sec1_t;
sec2<=sec2_t;
end process;
end rt1;