szsz.tan.rpt

该文件是用VHDL变成实现的数字钟程序

; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; hour2_t[3]                                                    ; hour2_t[3]                                                    ; clk        ; clk      ; None                        ; None                      ; 1.200 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; hour2_t[2]                                                    ; hour2_t[2]                                                    ; clk        ; clk      ; None                        ; None                      ; 1.200 ns                ;
+-------+------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                       ;
+-------+--------------+------------+---------------------------------------------------------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From                                                          ; To       ; From Clock ;
+-------+--------------+------------+---------------------------------------------------------------+----------+------------+
; N/A   ; None         ; 14.800 ns  ; hour2_t[3]                                                    ; hour2[3] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; hour2_t[2]                                                    ; hour2[2] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; hour2_t[1]                                                    ; hour2[1] ; clk        ;
; N/A   ; None         ; 12.600 ns  ; hour2_t[0]                                                    ; hour2[0] ; clk        ;
; N/A   ; None         ; 12.300 ns  ; lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; hour1[3] ; clk        ;
; N/A   ; None         ; 12.300 ns  ; lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; hour1[2] ; clk        ;
; N/A   ; None         ; 12.300 ns  ; lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; hour1[1] ; clk        ;
; N/A   ; None         ; 12.300 ns  ; lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; hour1[0] ; clk        ;
+-------+--------------+------------+---------------------------------------------------------------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Thu Nov 13 16:13:13 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off szsz -c szsz
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 75.19 MHz between source register "lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" and destination register "lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" (period= 13.3 ns)
    Info: + Longest register to register delay is 11.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A45; Fanout = 4; REG Node = 'lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(1.000 ns) + CELL(2.200 ns) = 3.200 ns; Loc. = LC6_A46; Fanout = 1; COMB Node = 'process0~54'
        Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 5.300 ns; Loc. = LC1_A46; Fanout = 3; COMB Node = 'process0~0'
        Info: 4: + IC(1.100 ns) + CELL(1.700 ns) = 8.100 ns; Loc. = LC8_A45; Fanout = 3; COMB Node = 'hour1_t~39'
        Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 10.000 ns; Loc. = LC6_A45; Fanout = 4; COMB Node = 'hour1_t~39_wirecell'
        Info: 6: + IC(0.200 ns) + CELL(1.300 ns) = 11.500 ns; Loc. = LC1_A45; Fanout = 6; REG Node = 'lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 8.800 ns ( 76.52 % )
        Info: Total interconnect delay = 2.700 ns ( 23.48 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_A45; Fanout = 6; REG Node = 'lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: - Longest clock path from clock "clk" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_A45; Fanout = 4; REG Node = 'lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tco from clock "clk" to destination pin "hour2[3]" through register "hour2_t[3]" is 14.800 ns
    Info: + Longest clock path from clock "clk" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_A46; Fanout = 4; REG Node = 'hour2_t[3]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 11.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A46; Fanout = 4; REG Node = 'hour2_t[3]'
        Info: 2: + IC(3.200 ns) + CELL(8.600 ns) = 11.800 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'hour2[3]'
        Info: Total cell delay = 8.600 ns ( 72.88 % )
        Info: Total interconnect delay = 3.200 ns ( 27.12 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 128 megabytes
    Info: Processing ended: Thu Nov 13 16:13:16 2008
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:01