counter.vhd

含有各类寄存器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
	Port (
		CLK	: in std_logic;
--		rst	: in std_logic;
		LEDG	: out std_logic;
		hs		: out std_logic;
		vs		: out std_logic;
		r		: out std_logic;
		g		: out std_logic;
		b		: out std_logic;
		digit	: out std_logic_vector(3 downto 0);
		LED	: buffer std_logic_vector(6 downto 0);
		dout	: out std_logic_vector(7 downto 0)
		);
end counter;

architecture Behavioral of counter is

--------------------------------------------------------------------------------
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--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
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--                                                                            --
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--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
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--                                                                            --
--     Xilinx products are not intended for use in life support               --
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--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2004 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component core_counnt
	port (
	Q: OUT std_logic_VECTOR(15 downto 0);
	CLK: IN std_logic;
	UP: IN std_logic;
	LOAD: IN std_logic;
	L: IN std_logic_VECTOR(15 downto 0);
	CE: IN std_logic;
	ACLR: IN std_logic);
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of core_counnt: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of core_counnt: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.


-- You must compile the wrapper file core_counnt.vhd when simulating
-- the core, core_counnt. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

component vga_16 is
    Port ( clk : in std_logic;
           hs : out std_logic;
           vs : out std_logic;
           r : out std_logic;
           g : out std_logic;
           b : out std_logic;
		 	  innum  : in std_logic_vector(15 downto 0);
			  innum0 : in std_logic_vector(15 downto 0); 
           innum1 : in std_logic_vector(6 downto 0);
           innum2 : in std_logic_vector(6 downto 0);
           innum3 : in std_logic_vector(6 downto 0);
		     innum4 : in std_logic_vector(6 downto 0));
end component;

signal count,Q,L: std_logic_vector( 15 downto 0);
signal CLKIN, rst, CE,LOAD,UP: std_logic;
signal N: std_logic_vector( 23 downto 0);
signal HEX: std_logic_vector(3 downto 0);
signal innum1 :  std_logic_vector(6 downto 0);
signal innum2 :  std_logic_vector(6 downto 0);
signal innum3 :  std_logic_vector(6 downto 0);
signal innum4 :  std_logic_vector(6 downto 0);
begin

rst<='1';
CE<='1';
LEDG<='1';

U1: vga_16 port map(clk,hs,vs,r,g,b,count, count,innum1,innum2,innum3,innum4);
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
U2 : core_counnt
		port map (
			Q => Q,
			CLK => CLKin,
			UP => UP,
			LOAD => LOAD,
			L => L,
			CE => CE,
			ACLR => rst);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
process(CLK)
begin
if CLK'event and CLK='1' then
	N<=N+1;
end if;
end process;

CLKIN<=N(23);

process (CLKIN, rst) 
begin
   if rst='0' then 
      count <= (others => '0');
   elsif CLKIN='1' and CLKIN'event then
      if CE='1' then
         count <= count + 1;
      end if;
   end if;
end process;
 

dout<= count(7 downto 0);

process(clk,rst,N,count)
begin
if rst='0' then
	digit<=(others=>'1');
elsif CLK'event and CLK='1' then
	case N(19 downto 18) is
	when "00" => digit<="1110";
					 HEX<=count(3 downto 0);
					 innum1<=LED;
	when "01" => digit<="1101";
					 HEX<=count(7 downto 4);
					 innum2<=LED;
	when "10" => digit<="1011";
					 HEX<=count(11 downto 8);
					 innum3<=LED;
	when "11" => digit<="0111";
					 HEX<=count(15 downto 12);
					 innum4<=LED;
	when others => null;
	end case;
end if;
end process;
   
    with HEX SELect
   LED<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
 
    

end Behavioral;